plz show all work! 2.28 The 74HC138 is a 3-t0-8 decoder with a logic diagram as

Question

plz show all work!

2.28 The 74HC138 is a 3-t0-8 decoder with a logic diagram as shown below. (a) Write hehavioral VHDL model for this circuit using a case statement. (b) Write dataflow VHDL model for this circuit using the corresponding logical equations (as in Figure 257 . (e) Make a structural VHDL model for this circuit (as in Figure 2-58) using AND gates and inverters A2 Y7 AI A0 Y4 El F3 YI 2.34 A synchronous (4-bi) up/down decade counter with auiput @ woiks as follows: All state changes occur on the rising edge of the CL.K inout, excent the asnouse

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder3x8 is
Port ( i : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder3x8;

architecture Behavioral of decoder3x8 is

begin

process(i)
begin
case i is
when "111" => y<="00000001";
when "110" => y<="00000010";
when "101" => y<="00000100";
when "100" => y<="00001000";
when "011" => y<="00010000";
when "010" => y<="00100000";
when "001" => y<="01000000";

when "000" => y<="10000000";
when others => null;
end case;
end process;
end Behavioral;

// Data flow VHDL

module decoder(d,x,y,z);
output [7:0] d;
input x,y,z;
assign d[0] = ~x & ~y & ~z;
assign d[1] = ~x & ~y & z;
assign d[2] = ~x & y & ~z;
assign d[3] = ~x & y & z;
assign d[4] = x & ~y & ~z;
assign d[5] = x & ~y & z;
assign d[6] = x & y & ~z;
assign d[7] = x & y & z;
endmodul

//This is the Stimulus part.
module stimulus;
wire [7:0]d;
reg x,y,z;

decoder my_decoder(d,x,y,z);
initial
begin
x=0;y=0;z=0;
#10 x=0; y=0; z=1;
#10 x=0; y=1; z=0;
#10 x=0; y=1; z=1;
#10 x=1; y=0; z=0;
#10 x=1; y=0; z=1;
#10 x=1; y=1; z=0;
#10 x=1; y=1; z=1;
#10 $stop;
#10 $finish;
end

endmodule

// structural VHDL model

library ieee;

use ieee.std_logic_1164.all;

entity andGate is

port( A, B, C : in std_logic;

F : out std_logic);

end andGate;

//architecture func of andGate is

begin

F <= A and B and C;

end func;

//*============================

//This is the NOT gate

library ieee;

use ieee.std_logic_1164.all;

entity notGate is

port( inPort : in std_logic;

outPort : out std_logic);

end notGate;

//architecture func of notGate is

begin

outPort <= not inPort;

end func;

//*=======================*======================

library ieee;

use ieee.std_logic_1164.all;

entity Decoder_3to8 is

port( A0, A1, A2 : in std_logic;

D0, D1, D2, D3, D4, D5, D6, D7 : out std_logic);

end Decoder_3to8;

architecture func of Decoder_3to8 is

component andGate is //import AND Gate entity

port( A, B, C : in std_logic;

F : out std_logic);

end component;

component notGate is //import NOT Gate entity

port( inPort : in std_logic;

outPort : out std_logic);

end component;

signal invA0, invA1, invA2 : std_logic;

begin

GI1: notGate port map(A0, invA0);

GI2: notGate port map(A1, invA1);

GI3: notGate port map(A2, invA2);

//the outputs

GA1: andGate port map(invA0, invA1, invA2, D0);

GA2: andGate port map( A0, invA1, invA2, D1);

GA3: andGate port map(invA0, A1, invA2, D2);

GA4: andGate port map( A0, A1, invA2, D3);

GA5: andGate port map(invA0, invA1, A2, D4);

GA6: andGate port map( A0, invA1, A2, D5);

GA7: andGate port map(invA0, A1, A2, D6);

GA8: andGate port map( A0, A1, A2, D7);

end func;

// test bench

library ieee;

use ieee.std_logic_1164.all;

--declare entity: no inputs, no outputs

entity Decoder_3to8_tb is

end Decoder_3to8_tb;

-- Describe how to test the Three-Eight-Decoder

architecture tb of Decoder_3to8_tb is

--pass Decoder_3to8 entity to the testbench as component

component Decoder_3to8 is

port( A0, A1, A2 : in std_logic;

D0, D1, D2, D3, D4, D5, D6, D7 : out std_logic);

end component;

signal A0, A1, A2, D0, D1, D2,

D3, D4, D5, D6, D7 : std_logic;

begin

-- map the testbench signals to the ports

-- of the Decoder_3to8

mapping: Decoder_3to8

port map(A0, A1, A2, D0, D1, D2, D3, D4, D5, D6, D7);

process

variable errCnt : integer := 0;--variable to track errors

begin

//TEST 0

A0 <= '1';

A1 <= '0';

A2 <= '1';

wait for 15 ns;

assert(D0 = '0') report "Error 0" severity error;

assert(D1 = '0') report "Error 0" severity error;

assert(D2 = '0') report "Error 0" severity error;

assert(D3 = '0') report "Error 0" severity error;

assert(D4 = '0') report "Error 0" severity error;

assert(D5 = '1') report "Error 0" severity error;

assert(D6 = '0') report "Error 0" severity error;

assert(D7 = '0') report "Error 0" severity error;

if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '0' or

D4 /= '0' or D5 /= '1' or D6 /= '0' or D7 /= '0') then

errCnt := errCnt + 1;

end if;

//TEST 1

A0 <= '1';

A1 <= '1';

A2 <= '1';

wait for 15 ns;

assert(D0 = '0') report "Error 1" severity error;

assert(D1 = '0') report "Error 1" severity error;

assert(D2 = '0') report "Error 1" severity error;

assert(D3 = '0') report "Error 1" severity error;

assert(D4 = '0') report "Error 1" severity error;

assert(D5 = '0') report "Error 1" severity error;

assert(D6 = '0') report "Error 1" severity error;

assert(D7 = '1') report "Error 1" severity error;

if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '0' or

D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '1') then

errCnt := errCnt + 1;

end if;

//TEST 2

A0 <= '1';

A1 <= '1';

A2 <= '0';

wait for 15 ns;

assert(D0 = '0') report "Error 2" severity error;

assert(D1 = '0') report "Error 2" severity error;

assert(D2 = '0') report "Error 2" severity error;

assert(D3 = '1') report "Error 2" severity error;

assert(D4 = '0') report "Error 2" severity error;

assert(D5 = '0') report "Error 2" severity error;

assert(D6 = '0') report "Error 2" severity error;

assert(D7 = '0') report "Error 2" severity error;

if(D0 /= '0' or D1 /= '0' or D2 /= '0' or D3 /= '1' or

D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '0') then

errCnt := errCnt + 1;

end if;

//TEST 3

A0 <= '0';

A1 <= '1';

A2 <= '0';

wait for 15 ns;

assert(D0 = '0') report "Error 3" severity error;

assert(D1 = '0') report "Error 3" severity error;

assert(D2 = '1') report "Error 3" severity error;

assert(D3 = '0') report "Error 3" severity error;

assert(D4 = '0') report "Error 3" severity error;

assert(D5 = '0') report "Error 3" severity error;

assert(D6 = '0') report "Error 3" severity error;

assert(D7 = '0') report "Error 3" severity error;

if(D0 /= '0' or D1 /= '0' or D2 /= '1' or D3 /= '0' or

D4 /= '0' or D5 /= '0' or D6 /= '0' or D7 /= '0') then

errCnt := errCnt + 1;

end if;

-------------- SUMMARY -------------

if(errCnt = 0) then

assert false report "Good!" severity note;

else

assert false report "Error!" severity error;

end if;

end process;

end tb;

--------------------------------------------

configuration cfg_tb of Decoder_3to8_tb is

for tb

end for;

end cfg_tb;

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