On an ARMv7-M processor, assuming that [R1] = 0x010E0C2D, [R2] = 0xFDB97531, [R3
ID: 3884591 • Letter: O
Question
On an ARMv7-M processor, assuming that [R1] = 0x010E0C2D, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0, [V-bit] = 1, predict the 32-bit [R1], [N-bit], [Z-bit], and [C-bit] after an ARM instruction is executed in EACH case. (These instructions are NOT executed one after the other; instead, each instruction starts with the initial conditions given in the statement.)
(a) MOVS R1, #0xFAB
(b) MOVS R1, R2, ASR #3
(c) MVNS R1, #0x2FC
(d) MVNS R1, R2, LSL R3
(e) MOVS R1, R2, RRX
(f) RORS R1, R2, #5
(g) LSRS R1, R2, R3
(h) MVNS R1, R2
Explanation / Answer
First, Let us see what does each instruction do:
MOV{S} {Condition} Rd, Op2
This instruction Moves data of Op2 into Rd
S - optional: When S is selected, conditional flags, N and Z are updated based on result. C is not affected, V is not affected.
Condition - optional condition if required
MVN{S} {Condition} Rd, Op2
This instruction performs bitwise NOT operation on Data in Op2 and stores it in Rd
S and condition are same as above.
ROR{S}{Condition} Rd [, Rs] [, Op2]
ROR Rd, Rs
This instruction Rotates the bits in Rd by the number present in Rs. The bits rotated at the right end are stored in the left before the MSB.
ROR Rd, #imm
This instruction Rotates the bits in Rd by the value #imm. The bits rotated at the right end are stored in the left before the MSB.
ROR Rd, Rs, #imm
This instruction Rotates the bits in Rs by the value #imm and stores it in Rd. The bits rotated at the right end are stored in the left before the MSB.
ROR Rd, Rs1, Rs2
This instruction Rotates the bits in Rs1 by the value present in Rs2 and stores it in Rd. The bits rotated at the right end are stored in the left before the MSB.
S - optional: If this is selected, the conditional flags, N, Z are updated based on the result. V is unaffected. C is unaffected is shift value is 0. Otherwise, It stores the last bit shifted right.
LSR{S}{Condition} Rd [, Rs] [, Op2]
This instruction is similar to above instruction but the right shifted values are discarded and zeroes are prepended before MSB
ASR{S}{Condition} Rd [, Rs] [, Op2]
This instruction is similar to LSR but the MSB is extended to previous bits
(a) MOVS R1, #0xFAB
before execution:
[R1] = 0x010E0C2D, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x00000FAB, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 0
(b) MOVS R1, R2, ASR #3
This instruction is equivalent to ASR R1, R2, #3
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0xFFB72EA6, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
(c) MVNS R1, #0x2FC
before execution:
[R1] = 0x010E0C2D, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0xFFFFFD03, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
(d) MVNS R1, R2, LSL R3
This instruction is equivalent to LSL R1, R2, R3
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x68ACEFFF, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1
(e) MOVS R1, R2, RRX
This instruction is equivalent to RRXS R1, R2
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x7EDCBA98, [R2] = 0xFDB97531, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1
(f) RORS R1, R2, #5
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x8FEDCBA9, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 1
(g) LSRS R1, R2, R3
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x000FDB97, [R2] = 0xFDB97531, [R3] = 0x0000000C, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1
(h) MVNS R1, R2
before execution:
[R1] = 0x010E0C2D, [R2] = 0xFDB97531, [N-bit] = 1, [Z-bit] = 0, [C-bit] = 0
after execution:
[R1] = 0x02468ACE, [R2] = 0xFDB97531, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 0
I hope everything is clear. Do upvote :)
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