A certain Processor has the following relevant specs: Clock cycle: 1 time unit P

Question

A certain Processor has the following relevant specs:
Clock cycle: 1 time unit
Pipelined: yes
Pipeline Stages: 6, assume all stages are of equal duration, and that each stage takes 1 Clock cycle Stage actions: FI, DI, CO, FO, EI, WO (see textbook page 446 for descriptions)

Memory access: SINGLE PORT, thus only one memory access operation can occur per clock cycle Instructions: assume ALL instructions go through ALL stages, stalling (causing a pipeline bubble) if necessary Registers: N/A
Cache: N/A

Bus: N/A ______________________________________________________________________________________

Given the following program segment written in (a certain) Assembly language: (operands are 1st and 2nd vars, the result is stored in the 3rd var...C=A and B) AND A, B, C
OR D, E, F

AND G, H, I

OR J, K, L

AND M, N, O

OR P, Q, R

considering hazards...

Repeat for the following program segment and again considering hazards:

NAND A, B, C

OR D, E, F

NOR E, F, G

XOR H, I, G

AND I, J, K N

AND K, L, K

Fetch instruction (FI): Read the next expected instruction into a buffer. Decode instruction (DI): Determine the opcode and the operand specifiers. Calculate operands (CO): Calculate the effective address of each source operand. This may involve displacement, register indirect, indirect, or other forms of address calculation. Fetch operands (FO): Fetch each operand from memory. Operands in regis- ters need not be fetched. ·Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified destination operand location. Write operand (WO): Store the result in memory.

Explanation / Answer

Operand Forwarding : In this technique the value of operand is given to the concerned stage of dependent instruction before it is stored.

In the above question, I2 is dependent on I0 and I1, and I3 is dependent on I2.

Instruction 0 is a MUL operation which take 3 clock cycles of CPU in the PO stage, and at any other stage it takes only 1 cycle.

Instruction 1 is a DIV operation which take 6 clock cycles of CPU in the PO stage, and at any other stage it takes only 1 cycle.

It can be noticed here that even when the OF stage was free in the 4th clock cycle, then also the instruction 1 was not given to it. This is a design issue. The operands should be fetched only if they are going to get operated or executed in the next cycle, else there is a possibility of data corruption. As PO stage was not free in the next cycle hence OF was delayed and was done for instruction 1 only just before 1 cycle of going to PO stage.

Instruction 2 is an ADD operation which take 1 clock cycles of CPU in all stages. But it is a dependent operation. it needs the operands which are provided by Instruction 0 and 1.

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