inputs: Q0 , D0 , D1 , N0 , N1 , N2 outputs : RQ0 , RD0 , RD1 , RN0 , RN1 , RN2
ID: 3865887 • Letter: I
Question
inputs: Q0 , D0 , D1 , N0 , N1 , N2 outputs : RQ0 , RD0 , RD1 , RN0 , RN1 , RN2 , NC
Q0 = A*E + A*D + A*C + A*B
D0= ~A*C*D*F+ C*E*D+ C*D+C*F + C*E*~F + A*C + A*B
D1= ~A*D+ E*F+ C*F+ C*E
N0 = ~A*D +E*F + C*E + C*F + ~C*E*F*~D + C*D*F + C*D*E
NC= A*~D*~E*F+ ~C*~D*~F + ~C*~D*~E +~D+ ~E*~F + ~C*~E+ ~C*~F + A*~C*~D*~E
N1= ~A*~C*D*E*F+ ~C*D+ ~C*E*F+ A*~C*D + ~C*E
N2= ~A*C*D*F + D*E*F + C*E*D
1) write Testbench code , Verilog for dataflow version of module. Timing Diagram for dataflow version of module. Verilog for structural version of module.Timing Diagram for structural version of module. and draw Schematic. thanks
Explanation / Answer
module tb_and_gate;
reg A,B;
wire Y;
and_gate a1 (.a(A) ,.b(B),.y(Y));
//Above style is connecting by names
initial begin
A =1'b0;
B= 1'b0;
#45 $finish;
end
always #6 A =~A;
always #3 B =~B;
always @(Y)
$display( "time =%0t INPUT VALUES: A=%b B =%b output value Y =%b",$time,A,B,Y);
endmodule
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