In this question, we will examine how pipelining affects the clock cycle time of
ID: 3851248 • Letter: I
Question
In this question, we will examine how pipelining affects the clock cycle time of the processor.Problems in this exercise assume that individual stages of the datapath have the following latencies:
Also, assume that instructions executed by the processor are broken down as follows:
a. What is the clock cycle time in a pipelined and non-pipelined processor?
b. What is the total latency of an LW instruction in a pipelined and non-pipelined processor?
c. Assuming there are no stalls or hazards, what is the utilization of the data memory?
d. Assuming there are no stalls or hazards, what is the utilization of the write-register port of the“Registers” unit?
IF ID EX MEM WB 250ps 350ps 150ps 300ps 200psExplanation / Answer
C. Utilization of data memory is done by only "LW and SW"
So, the utilization = LW + SW
= 20% + 15%
= 35%
Utilization of the data memory is 35% of the clock cycles.
D. Utilization of write-register port is done by only "ALU and LW"
So, th utilization = ALU + LW
= 45% + 20%
= 65%
Utilization of write-regiter port is 65% of the clock cycles.
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