In this question we would like to design a 4-bit BCD adder. It is similar to the

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In this question we would like to design a 4-bit BCD adder. It is similar to the 4-bit binary except we limit our input numbers of A and B to number 9 and accordingly the largest sum output is going to be number 18. However, in order to display the addition result on two separate 7-segment displays, we need to add number 6 to the output, if the output is between 10 to 18. As an example, if we add 8 + 6 = 14, in binary = 1110. So if we added 6, in binary = 0001 0100. So if we connect each of these 2 groups of 4-bit to a BCD to a 7-segment decoder and a display as we did in lab03, the first group (0001) will display #1 while the second group (0100) will display #4. The digital logic circuit to correct (add 6) in the sum is between 10 and 18 is shown below. We are going to design a module, call it 'correct_BCD', that will correct the adder result by adding #6 if the result is between 10 and 18. Let us say the 5-bit output from the BCD adder is {Cout, S3, S2, S1, S0}. We need to add 6 only if the ORing of Cout with (S3 S2 + S3 S1) gives one. 1. Design and implement a Verilog code for the BCD correction. Complete the blue lines below bearing in mind that the conditional operator is denoted by a "?" so don't delete it accidentally; module correct_BCD (LEDR, SW); input [4:0] SW;//Cout=SW[4], Sum=SW[3:0] output [4:0] LEDR; wire [4:0] correct; assign correct = SW[?] | ((SW[?] & SW[?]) | (SW[?] & SW[?]));//We need to add 6 if [Cout = 1 or (S_3S_2 + S_3S_1)] assign LEDR = correct? (SW+6): SW;//use the conditional operator to test if correct = l then add 6 endmodule

Explanation / Answer

Edited Blue line is given below

assign correct = SW[4] | ((SW[3] & SW[2]) | (SW[3] & SW[1]));

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