Write a verilog code for the following. Design a transaction-based multipurpose

Question

Write a verilog code for the following. Design a transaction-based multipurpose processor that accepts inputs of the form (tag[1:0], operation[5:0], data[n-1:0]) and produces output in the form (tag[1:0], data[n-1:0]). The processor has a 8-entry tagged register file that holds n-bit intermediate results. The tags are used by the external circuit to associate results with operands. The exact behavior of tags will be described below. The module has inputs clk, reset, i_valid, i_tag, operation, and i_data. The outputs are o_valid, o_tag, o_data, and ready. These are described below: clk, reset: the system clock and reset i_valid: signals to the circuit that the input represents a valid instruction i_tag, operation, i_data: the tag, operation, and data associated with the input o_tag, o_data: the data output on a READ o_valid: signals to the external system that a READ value is on the output ready: signals to the external system that an instruction can be accepted The operations supported by the processor are shown in the following table. The notation rrr indicates a 3-bit register number and d[n-1:0] is the input data. Operation format Description STI R      000rrr     Store immediate value to register R (Rd) SUB R    001rrr     Subtract Immediate Value from Register R (RR-d) EOR R   010rrr     Exclusive OR Immediate with R (RR^d) AND R   011rrr     AND immediate with R (RR&d) SHR R   100rrr     Shift R Right by d[1:0] SHL R    101rrr     Shift R Left by d[1:0] TAG R   110rrr     The TAG associated with R is changed to the least significant bits of the input data (TAGRd[1:0]) READ R 111rrr   Output value of R (with tag) Tags are used by the external system to associate results of computations. Each operation and register has a 2-bit tag that is used only by the external system. However, your processor must maintain and handle the tags correctly. The first four operations (STI,SUB,EOR,AND) and TAG overwrite the tag in the register file with the input tag.    All other operations leave the tag unchanged. There is no restriction on the latency of your system (you processor can take 1 cycle or more to complete an operation). However, your circuit must be able to accept a new input on every clock cycle for at least 20 clock cycles before deasserting ready.

Explanation / Answer

Equipment depiction dialects, for example, Verilog vary from programming dialects since they incorporate methods for portraying the spread time and flag qualities (affectability). There are two sorts of task administrators; a blocking task (=), and a non-blocking (<=) task. The non-blocking task enables fashioners to portray a state-machine refresh without expecting to proclaim and utilize impermanent capacity factors. Since these ideas are a piece of Verilog's dialect semantics, planners could rapidly compose depictions of substantial circuits in a generally minimal and compact frame. At the season of Verilog's presentation (1984), Verilog spoke to a colossal efficiency change for circuit architects who were at that point utilizing graphical schematic catch programming and extraordinarily composed programming projects to archive and reproduce electronic circuits.
The architects of Verilog needed a dialect with punctuation like the C programming dialect, which was at that point generally utilized as a part of designing programming improvement. Like C, Verilog is case-delicate and has a fundamental preprocessor (however less complex than that of ANSI C/C++). Its control stream watchwords (if/else, for, while, case, and so forth.) are proportional, and its administrator priority is good with C. Syntactic contrasts include: required piece widths for variable announcements, division of procedural squares (Verilog utilizes start/end rather than wavy props {}), and numerous other minor contrasts. Verilog requires that factors be given a distinct size. In C these sizes are accepted from the "sort" of the variable (for example a number sort might be 8 bits).
A Verilog configuration comprises of a chain of command of modules. Modules typify outline chain of command, and speak with different modules through an arrangement of announced info, yield, and bidirectional ports. Inside, a module can contain any blend of the accompanying: net/variable presentations (wire, reg, whole number, and so forth.), simultaneous and successive explanation pieces, and cases of different modules (sub-chains of command). Consecutive proclamations are put inside a start/end piece and executed in successive request inside the square. In any case, the squares themselves are executed simultaneously, making Verilog a dataflow dialect.
Verilog's idea of "wire" comprises of both flag values (4-state: "1, 0, drifting, vague") and flag qualities (solid, feeble, and so on.). This framework permits unique demonstrating of shared flag lines, where different sources drive a typical net. At the point when a wire has different drivers, the wire's (intelligible) esteem is settled by an element of the source drivers and their qualities.
A subset of explanations in the Verilog dialect are synthesizable. Verilog modules that adjust to a synthesizable coding style, known as RTL (enroll exchange level), can be physically acknowledged by blend programming. Union programming algorithmically changes the (conceptual) Verilog source into a netlist, a legitimately equal portrayal comprising just of basic rationale primitives (AND, OR, NOT, flip-flops, and so on.) that are accessible in a particular FPGA or VLSI innovation. Facilitate controls to the netlist at last prompt a circuit creation diagram, (for example, a photograph cover set for an ASIC or a bitstream petition for a FPGA).

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