(a) You are building an instruction cache for a MIPS processor. It has a total c

Question

(a) You are building an instruction cache for a MIPS processor. It has a total capacity of 4C = 2c + 2 bytes. It is N= 2n - way set associative (N greaterthanorequalto 8), with a block size of b = 2b' bytes (b greaterthanorequalto 8). Give your answers to the following questions in terms of these parameters. Here is the picture of the physical memory address: Which bits of the physical address are used to select a word within a block? Which bits of the physical address are used to select the set within the cache? How many tag bits are needed per block? How many total bits are needed for the tag storage array portion of the cache?

Explanation / Answer

#define MAX_SIZE 256 #define IF(a) if (a) { #define ENDIF } typedef struct { unsigned char red; // 'unsigned char' is an unsigned, 8-bit int unsigned char green; unsigned char blue; unsigned char alpha; } RGBa; // these allocate storage int i; int N = 20; char prompt[] = "Enter an integer:"; int A[MAX_SIZE]; int* pBArray; int BSize; RGBa background = {0xff, 0xff, 0xff, 0x0};

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