For a computer architecture with multi-level paging, a page size of 4KB and 64-b

Question

For a computer architecture with multi-level paging, a page size of 4KB and 64-bit physical and virtual addresses: a. What is the smallest possible size for a page table entry, rounded up to a power of 2? b. Using your results above, and assuming a requirement that each page table fits into a single page, how many levels of page tables would be required to completely map the 64-bit virtual address space? The following figures show the Solaris Virtual Memory Layout on different hardware platforms:

Explanation / Answer

A) First we need to find out the page offset  by calculating log2(page size in bytes). Here the, page size is 4KBytes, so log2(4*2^10) is 12; that is, page offset is 12 bits

Then we are going to calculate  Physical Page Number (PPN) by subtracting page offset from total number of bits allocated for physical address.
Here Physical address = 64 bit
PPN = 64 - 12 = 52.

Now to calcluate Page table entry we need to add valid bit, protection bit, etc. But to calculate minimum we make it 0.

At last we will calculate the number of page entries in the page table.

To get this we need to subtract page offset from the total number of bits we have for the virtual page number; that is, 64 - 12 = 52 i.e. we need 2^52 entries to represent the full range of the virtual addresses.

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