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2. Consider the following assembly language code: I0: ADD R4 = R1 + R0; I1: SUB

ID: 3822447 • Letter: 2

Question

2. Consider the following assembly language code:

I0: ADD R4 = R1 + R0;

I1: SUB R9 = R3 - R4;

I2: ADD R4 = R5 + R6;

I3: LDW R2 = MEM[R3 + 100];

I4: LDW R2 = MEM[R2 + 0];

I5: STW MEM[R4 + 100] = R2;

I6: AND R2 = R2 & R1;

Assuming no data forwarding, draw the time sequence pipeline diagram and calculate the number of clock cycles needed to complete the whole sequence of instruction.

Assuming forwarding, draw the time sequence pipeline diagram and calculate the number of clocl cycles needed to complete the whole sequence of instruction.

3. Rearrange the following code to avoid/reduce the stall clock cycles

add $3,$2,$1

lw $4,4($3)

addi $6,$4,1

sub $8,$3,$1

Explanation / Answer

2.

Let us consider the following assembly language code:

I0: ADD R4 = R1 + R0;

I1: SUB R9 = R3 - R4;

I2: ADD R4 = R5 + R6;

I3: LDW R2 = MEM[R3 + 100];

I4: LDW R2 = MEM[R2 + 0];

I5: STW MEM[R4 + 100] = R2;

I6: AND R2 = R2 & R1;

The time sequence pipeline diagram (no data forwarding)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

I0

IF

ID

EX

MEM

WB

I1

IF

ID

X

EX

MEM

WB

I2

IF

ID

X

X

EX

MEM

WB

I3

IF

ID

X

X

EX

MEM

WB

I4

IF

ID

X

X

X

EX

MEM

WB

I5

IF

X

X

X

ID

EX

MEM

WB

I6

X

X

X

IF

ID

EX

MEM

WB

The number of clock cycles needed to complete the whole sequence of instruction is 13.

The time sequence pipeline diagram (with forwarding)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

I0

IF

ID

EX

MEM

WB

I1

IF

ID

EX

MEM

WB

I2

IF

ID

EX

MEM

WB

I3

IF

ID

EX

MEM

WB

I4

IF

ID

X

EX

MEM

WB

I5

IF

X

ID

EX

MEM

WB

I6

X

IF

ID

EX

MEM

WB

The number of clock cycles needed to complete the whole sequence of instruction is 11.

3. The given code is rearranged below to avoid stall clock cycles:

add $3,$2,$1

lw $4,4($3)

sub $8,$3,$1

addi $6,$4,1

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

I0

IF

ID

EX

MEM

WB

I1

IF

ID

X

EX

MEM

WB

I2

IF

ID

X

X

EX

MEM

WB

I3

IF

ID

X

X

EX

MEM

WB

I4

IF

ID

X

X

X

EX

MEM

WB

I5

IF

X

X

X

ID

EX

MEM

WB

I6

X

X

X

IF

ID

EX

MEM

WB