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2. (50 POINTS) Install and run Icarus Verilog (iverilog simulator together with

ID: 3818457 • Letter: 2

Question

2. (50 POINTS) Install and run Icarus Verilog (iverilog simulator together with gtkwave output viewer on your computer. You may find and freely install this tool online. A collection of sample Verilog files (though for a totally different functionality are provided as an attachment to this homework so as to help you. Submit ALL your verilog files for this question so that we run them and make sure that they compile and execute. Please make sure to also provide a README.TXT to guide us on how to execute your program and view the monitor as well as gtkwave output. 2.A. (30 POINTS Write a program to get two 4-bit inputs and perform logical and of these two inputs and display the output. Provide a screenshot of your verilog programs. 2.B. (10 POINTS Compile and execute the program on one set of sample input values you arbitrarily select for the two inputs. Display the output to the standard output (monitor) Provide a screenshot of your monitor display. 2.C. (10 POINTSO Open gtkwave and view the waveforms of input signals and the output signal. If necessary, adjust settings of the current view to display the waveforms better. Provide a screenshot of your gtkwave display

Explanation / Answer

module main;

initial
begin

wire c;

c=a&b;

output c;

  
   $finish;
end
endmodul

module Bitwise (A, B, Y);

                 input [6:0] A;

                 input [5:0] B;

                 output [6:0] Y;

                 reg [6:0] Y;

                 always @(A or B)

                 begin

                                  Y(0)=A(0)&B(0); //binary AND

                                  Y(1)=A(1)|B(1); //binary OR

                                  Y(2)=!(A(2)&B(2)); //negated AND

                                  Y(3)=!(A(3)|B(3)); //negated OR

                                  Y(4)=A(4)^B(4); //binary XOR

                                  Y(5)=A(5)~^B(5); //binary XNOR

                                  Y(6)=!A(6); //unary negation

                 end

endmodule

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