4.17 This exercise explores how exception handling affects pipeline design. The

Question

4.17 This exercise explores how exception handling affects pipeline design. The
first three problems in this exercise refer to the following two instructions:
Instruction 1: BNE R1, R2,

Instruction 2: Label LW R1, 0(R1)

4.17.1 [5] <§4.9> Which exceptions can each of these instructions trigger? For
each of these exceptions, specify the pipeline stage in which it is detected.

4.17.2 [10] <§4.9> If there is a separate handler address for each exception, show
how the pipeline organization must be changed to be able to handle this exception.
You can assume that the addresses of these handlers are known when the processor
is designed.

4.17.3 [10] <§4.9> If the second instruction is fetched right aft er the fi rst
instruction, describe what happens in the pipeline when the fi rst instruction causes
the fi rst exception you listed in 4.17.1. Show the pipeline execution diagram from
the time the fi rst instruction is fetched until the time the fi rst instruction of the
exception handler is completed.

4.17.4 [20] <§4.9> In vectored exception handling, the table of exception handler
addresses is in data memory at a known (fi xed) address. Change the pipeline to
implement this exception handling mechanism. Repeat 4.17.3 using this modifi ed
pipeline and vectored exception handling.

4.17.5 [15] <§4.9> We want to emulate vectored exception handling (described
in 4.17.4) on a machine that has only one fi xed handler address. Write the code
that should be at that fi xed address. Hint: this code should identify the exception,
get the right address from the exception vector table, and transfer execution to that
handler.

Explanation / Answer

4.17:

instruction1   Instruction 2

BNE R1, R2, Label LW R1, 0(R2)

Consequence will be: The pipeline stage in which it is distinguished

INSTRUCTION 1                        INSTRUCTION 2

Invalid target address (EX) Invalid data address (MEM)

4.17.2:

If there is a distinct trainer address for each concession then Mux that select the next PC necessity have input added to it. Respectively input is a continuous address of an exclusion handler. The exception sensor necessity be additional to the suitable duct stage and the output of these sensors must be used to control the pre- Pc Mux, and to convert to NOPs instruction that are already in the pipeline overdue the exception activating instruction.

4.17.3:

uncertainty the second instruction is complete right after the first instruction in this condition Instructions are fetched usually until the exception is detected. When the exception is detected, all instructions that are in the pipeline afterward the first instruction must be reformed to NOP. As a result, the second teaching never finishes and does not affect pipeline state. In the cycle that directly follows the cycle in which the exclusion is detected, the computer will make the first instruction of the exclusion trainer.

4.17.4:

This method needs us to fetch the address of the handler from memory. We must add the code of the exception to the address of the exception vector table, read the handler’ 5 address from memory, and hurdle to the address. One way of responsibility this is to grip it as a special instruction that computer the address in EX, loads the handlers’ address in MEM , and set the Pc in WB.

4.17.5:

We essential a special instruction that lets us to change a value from the Reason register to a general-purpose register. We must first but the general- determination register, load the Cause register into it, add the address of the vector bench to it, use the result as an address for a weight that becomes the address of the right exclusion handler from memory, and lastly jump to that trainer.

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