4.17 This exercise explores how exception handling affects pipeline design. The

Question

4.17 This exercise explores how exception handling affects pipeline design. The first three problems in this exercise refer to the following two instructions: Instruction 1 Instruction 2 BNE R1, R2, Label LW R1, O(R1) 4.17.1 [5] Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected. 4.17.2 [10] If there is a separate handler address for each exception, show how the pipeline organization must be changed to be able to handle this exception. You can assume that the addresses of these handlers are known when the processor is designed. (note in .2 don't "show", but describe how to fix.)

Explanation / Answer

4.17:

instruction1   Instruction 2

BNE R1, R2, Label LW R1, 0(R2)

Consequence will be: The pipeline stage in which it is distinguished

INSTRUCTION 1                        INSTRUCTION 2

Invalid target address (EX) Invalid data address (MEM)

4.17.2:

If there is a distinct trainer address for each concession then Mux that select the next PC necessity have input added to it. Respectively input is a continuous address of an exclusion handler. The exception sensor necessity be additional to the suitable duct stage and the output of these sensors must be used to control the pre- Pc Mux, and to convert to NOPs instruction that are already in the pipeline overdue the exception activating instruction.

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