2. (LO 4) Assume that the individual stages of the MIPs pipelined datapath have

Question

2. (LO 4) Assume that the individual stages of the MIPs pipelined datapath have the following latencies (Tis): IF latency 300 ps, ID 150 ps, Ex latency m 200ps, MEM latency latency WB latency 150 ps. Consider now the following sequence of instructions: 15 O lw 2, 4 ($t0) add $t3, $s1, $s2 sub Stl, $t4, t5 nmend for a single cycle design and the 30ct IS 01 z cot 300 t is o (a) (10 pts. Lo 4) What recede si ne ac instruct en e cause fini s 4 nus t uit for previous instruction sto (b) o pts.) If a pipelined design is used, derive the period (Tr) of this machine; derive also the execution time of the instruction sequence using this period. (1)(30) 2100 300

Explanation / Answer

The answer which you have mentioned is clock cycle time or clock cycle period. Clock cycle time is defined as the length of the cycle. But the question here asked is Clock rate. So, you need to reciprocate the cycle time;which gives you the clock rate. Therefore, the Clock rate is defined as the reciprocal of the cycle time. And,finally the answer will be 1/1100.

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