Write the VHDL code for test bench simulation For Y = A and B Fill out the missi

Question

Write the VHDL code for test bench simulation For

Y = A and B

Fill out the missing codes below?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity task1_tb is
-- Port ( );
end task1_tb;

architecture Behavioral of task1_tb is

--declaring the component
component task1
     Port ( a : in STD_LOGIC;
        b : in STD_LOGIC;
        y : out STD_LOGIC);
end component;

--declaring the signals needed
--these y,a,b signals are different from the
--internal ones of the component
signal y,a,b:  std_logic;

--signal to assign values to a and b
signal counter:  unsigned(1 downto 0):="00";

begin
-- component assignment
uut: task1 port map(
  a => a,
  b => b,
  y => y
);

--assign a (bit 1) and b (bit 0) to the counter bits so that
--all possible inputs are tested
--Enter your code here


  
--increments the counter using a process
--use a 20ns delay between each combination
--Enter your code here
   

--assign operation results to y
--Enter your code here

end Behavioral;

Explanation / Answer

Answer:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test --'test' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
PORT(
clk : IN std_logic;
count : OUT std_logic_vector(3 downto 0);
reset : IN std_logic
);
END COMPONENT;
--declare inputs and initialize them
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--declare outputs and initialize them
signal count : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
   clk => clk,
count => count,
reset => reset
);

-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
-- Stimulus process
stim_proc: process
begin
wait for 7 ns;
reset <='1';
wait for 3 ns;
reset <='0';
wait for 17 ns;
reset <= '1';
wait for 1 ns;
reset <= '0';
wait;
end process;

END;

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