Write the VHDL code for a flexible 5-bit add/subtract for signed numbers. It sho
ID: 3760108 • Letter: W
Question
Write the VHDL code for a flexible 5-bit add/subtract for signed numbers. It should do both addition and subtraction based on the add_sub input. The port description is as follows: 1. X, Y: 5 bit inputs. 2. Result: 5 bit output. Either (X+Y) or (X-Y) depending on in put. 3. add_sub If this input is One, then the Result should be the sum of inputs. Else, the result is X-Y. 4. zero_flag: It should go high Only when the result is Zero. 5. Overflow: It should go height onIy when the operation leads to an overflow, and therefor the result is wrong. Remember that with 5 bits you can show signed numbers from -16 to +15, so any data outside this range will set the overflow flag to high. You can refer to vhdl_notes.ppt for extra help as how to complete the VHDL code.Explanation / Answer
-- FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;
architecture bhv of Full_Adder is
begin
sum <= (X xor Y) xor Cin;
Cout <= (X and (Y or Cin)) or (Cin and Y);
end bhv;
========================================================
--5 bit Adder Subtractor
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
port( OP: in std_logic;
A,B : in std_logic_vector(4 downto 0);
R : out std_logic_vector(4 downto 0);
Cout, OVERFLOW : out std_logic);
end addsub;
architecture struct of addsub is
component Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end component;
signal C1, C2, C3, C4,C5: std_logic;
signal TMP: std_logic_vector(4 downto 0);
begin
TMP <= A xor B;
FA0:Full_Adder port map(A(0),TMP(0),OP, R(0),C1);-- R0
FA1:Full_Adder port map(A(1),TMP(1),C1, R(1),C2);-- R1
FA2:Full_Adder port map(A(2),TMP(2),C2, R(2),C3);-- R2
FA3:Full_Adder port map(A(3),TMP(3),C3, R(3),C4);-- R3
FA4:Full_Adder port map(A(4),TMP(4),C4, R(4),C5);-- R4
OVERFLOW <= C4 XOR C5 ;
Cout <= C5;
end struct;
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