The load function on a 54HC160 counter is asynchronous. TRUE FALSE A 50 MHz cloc

Question

The load function on a 54HC160 counter is asynchronous. TRUE FALSE A 50 MHz clock has a 10% duty cycle. How long during each period is the clock signal high (logic '1')? 20 ns 100 ns 5 ns 1 ns none of the above What is the maximum clock frequency of a ring counter made with 74LVC2g74 registers? (Assume VCC = 3.3V) 175 MHz 180 MHz 138.9 MHz 150.2 MHZ none of the above A latch circuit is implemented with NAND gates. Why is R = S = '0' considered an invalid input? It causes the latch to become metastable It produces glitches on the Q output It makes both the NAND gates consume excessive current It makes the Q and the Q-bar outputs have the same logic value

Explanation / Answer

1.) False. 54hc160 counter is synchronous

2.) time = 1/freq = 1/(50*10^-6) = 20 ns. For 10% duty cycle, clock signal will be high for 2 ns. Therefore, option e is correct.

3.) Maximum frequency of 74LVC2g74 according to its datasheet is 175 MHz. So, option a is correct.

4.) Because it makes the Q and Q-bar outputs have the same logic. Hence, option d is correct.

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