4) (10 pts) The quad-core multiprocessor shown in Figure 2 uses directory-based
ID: 3780436 • Letter: 4
Question
4) (10 pts) The quad-core multiprocessor shown in Figure 2 uses directory-based cache coherence implemented in the shared L2 cache. Each processor has an L1 write-back private cache. Three states are defined in the L1 cache: M (Modified), S (Shared), and l (invalid). For simplicity, each L1 cache is directly-mapped with four blocks, and each block holds two words (8 bytes). For clarity, the tag contains the full address in hexadecimal, while the data is shown in decimal The L2 cache is directly-mapped, shared by a cores, and split into two banks. Blocks whose physical addresses are multiple of 16 (0x10 in hexadecimal) are mapped to L2 cache bank 0, while the other blocks are mapped to L2 cache bank 1. Four presence bits are associated with each L2 cache block, to indicate which L1 cache has a copy of the L2 cache block. The L2 cache is sufficiently large and contains a superset of the L1 blocks (inclusion policy). Four states are associated with each L2 cache block: M (Modified by a processor), o (Owned by L2 and can be shared in L1), S (Shared clean block), and l (Invalid). The L2 Owned state indicates that a block was modified in L1 and later written back to L2. The L2 cache is updated but not memoryExplanation / Answer
a) P0 reads address 0X120
L2 Shared Cache Bank0 gets updated like below
Presence
State
tag
Block Data
1111
O
0x120
20
10
P0 processor of L1 Cache will be updated as below
Processor P0
State
Tag
Data
S
0x120
20
10
b) P3 writes address 0x124<-38
L2 shared cache Bank1 gets updated like below
Presence
State
tag
Block Data
0010
O
0x124
30
8
P3 processor of L1 Cache will be updated as below
Processor P3
State
Tag
Data
M
0x124
30
8
c) P2 reads address 0x128
L2 Shared Cache Bank1 gets updated like below
Presence
State
tag
Block Data
0010
O
0x128
0
11
P2 processor of L1 Cache will be updated as below
Processor P3
State
Tag
Data
M
0x128
30
8
d) P1 reads address 0x158
L2 Shared Cache Bank1 gets updated like below
Presence
State
tag
Block Data
1010
O
0x158
76
35
P1 processor of L1 Cache will be updated as below
Processor P3
State
Tag
Data
S
0x158
76
35
e) P1 writes address 0x11c<-14
L2 Shared Cache Bank1 gets updated like below
Presence
State
tag
Block Data
1000
O
0x11c
14
0
P1 processor of L2 Cache will be updated as below
Processor P1
State
Tag
Data
M
0x11c
14
0
Presence
State
tag
Block Data
1111
O
0x120
20
10
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