4 pts) 2. Assuming an Instruction cache rate for a program is 2%, and a Data cac
ID: 3828383 • Letter: 4
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4 pts) 2. Assuming an Instruction cache rate for a program is 2%, and a Data cache miss rate is 5%. If a miss is 100 cycles for all processor has a CPI of 2 without any memory stalls, and the miss penalty instructions are misses. Assume that 30% instructions load & stores, 50% of the ALUs and 20% of the instructions are are controls. (7 pts) 2.1 What is actual cPI with the possible cache misses? Assume that we have perfect data and instruction cache (no cache misses), what is the performance speed up of the CPU with the ideal perfect cache vs. the CPU with actual cache. (3 pts) 2.2 What if the processor is faster, but memory system is not. Suppose we speed up the CPI from 2 to 1 without changing the clock rate. What is the CPI ofthe system with cache misses? What is the performance speed up of the CPU with the ideal perfect cache vs. the CPU with actual cache? (4 pts) 2.3 What is your observation on the effect of the memory on the system performance?Explanation / Answer
given that
Instruction cache miss rate = 2%
Data cache miss rate = 5%
Processor cycles per instruction(CPI) = 2 (without memory stalls)
Miss penalty = 100 cycles
30% of instructions are loads and stores
2.1Assume I = total instruction count
Instruction miss cycles = I * 2% * 100 = 2*I
Data miss = I* 30% * 5% *100 = 1.55*I
Memory stall cycles = 1.55*I + 2*I = 3.55*I
CPU execution time per inst = 3.55 + 2 = 5.55, vs. 2 for perfect cache
Ideal CPI Performance = 5.55/2 = 2.775 faster for a system with a perfect cache
2.2 If we reduce based CPU to 1, a system with perfect cache will be
Using the same memory stall figure,
CPU exec time per instruction = 1+ 3.55 = 4.55, was 5.55,
so 5.55/4.55 = 1.219, so only 22% faster
2.3 Need to speed up memory: it’s the big problem here
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