Design the hardware for a left shifter that shifts an 8-brt number 2 bits to the

Question

Design the hardware for a left shifter that shifts an 8-brt number 2 bits to the left. For example, if A = 00011111. A Shifted = 01111100? Write -13, 5625 as a 11 bit signed-magnitude number with 7 integer bits and 4 fraction bits 10-bit 2's complement number with 5 integer bits and 5 fraction bits List The types of hazard one will have to consider in a pipelined processor. Also, list methods of taking care of those hazards. Consider memory storage of a 32-bit word stored at memory word 15 in a byte-addressable memory. Fill in the byte address values and the data values fields in the diagram below.

Explanation / Answer

4Q)

Hazards in Pipelining : A Pipeline Hazard is defined as a situation in which a correct program stopped to work correctly due to impementing the processor with pipeline.

Hazards reduce the performance from the ideal speedup gained by pipelining.

Types of Hazards :

Fundamental types of Hazards are 3 types. Those are :

1) Structural Hazards.

2) Data Hazards

3) Control Hazards

1) Structural Hazards :

Structural hazards occur when a single piece of hardware is used in more than one stage of the pipeline, so it's possible for two instructions to need it at the same time.

This hazard can be resolved by adding extra hardware.

2) Data Hazards :

Data Hazards occur when the pipeline changes the order of read/write accessing to operands so that the order differs from the order seen by sequentially executing instructions on the unpipelined machine. Data Hazards are caused by data dependences.

Data Hazards are of three types :

RAW : Read After Write Hazard.

This is the most common type of hazard

It occurs when the code as written, one instruction reads a location after an earlier instruction writes new data to it, but in the pipeline the write occurs after the read.

WAR : Write After Read Hazard.

It is reverse of RAW Hazard. In this hazard, in the code a write occurs after a read instruction,but the pipeline causes write to happen first.

WAW : Write After Write Hazard.

It is situation in which two write instructions occurs out of order.

We normally only consider it a WAW Hazard when there is no read instruction in between, if there is any read instruction then we have a RAW and/or WAR hazard to resolve, and then by the time we've gotten that straightened out the WAW has likely taken care of itself.

3. Control Hazards :

This Hazards arises from the pipelining of branches and other instructions that change the PC (Program Counter).

Resolving methods of Hazards :

There are 4 methods available to resolve the Hazards. Those are :

Forward, Add hardware, Stall, and Document (AKA Punt)

1) Forward :

It is works like this :

If the data is available somewhere, but is just not where we want it.

We can create extra data paths to Forward the data to where it is needed.

It doesn't slow the machie down and doesn't change semantics of the instruction set. So, it is best solution for the hazards.

2) Add hardware :

It is most suitable for Structural hazards. If a peice of hardware has to be used twice in an instruction, see if there is any way to duplicate the hardware.

3) Stall :

Sacrifice performance to prevent the hazard from occuring.

Stalling causes Bubbles.

We can simply make the later instruction wait until the hazard resolves itself. This is undesireable because it slows down the machine, but may be necessary.

Handling a hazard on waiting for data from memory by stalling would be an example.

4) Document (AKA punt) :

Define instruction sequences that are forbidden, or change the semantics of instructions, to account for the hazard.

For example delayed loads and delayed branches.

This is the worst solution, both because it results in obscure conditions on permissible instruction sequences, and (more importantly) because it ties the instruction set to a particular pipeline implementation.

A later implementation is likely to have to use forwarding or stalls anyway, while emulating the hazards that existed in the earlier implementation.

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