A non-pipelined version MIPS processor, currently use 5 stage datapath (IF ID EX
ID: 3771504 • Letter: A
Question
A non-pipelined version MIPS processor, currently use 5 stage datapath (IF ID EXE MEM WB, and base CPI 5).
Now a new way to optmize the hardware so now Clock speed is doubled, and the MEM phase can be eliminated in those instructions that don't need it. However, memory access speed has not changed, so at the new clock speed, all memory access now take twice as long in terms of clock cycles.
Calculate the speedup of new design.
insturction mix shown below:
Loads 20% Stores 10% ALU Ops 40% Branches 20% Other 10%Explanation / Answer
Answer:
The speed of instructions for the given new clock cycles is =
The speed of instructions for the given new clock cycles is =
Therefore, the speed up of the new design is twice that of the old design.
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.