2.3.4 Structural (Modular) Coding Structural or modular coding refers to first c
ID: 3733769 • Letter: 2
Question
2.3.4 Structural (Modular) Coding Structural or modular coding refers to first creating modules of logic blocks that are functionally independent of each other, and then “stitching up” these blocks into a circuit with a more complex overall function. One method of doing such hierarchical design in VHDL is shown in the below example where 1-bit full adders are used to build a 4-bit ripple carry adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add4bit is Port
( cin : in STD_LOGIC; x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end add4bit;
architecture Structure of add4bit is -- declare internal signals used to interconnect 1-bit adders: signal c1, c2, c3 : STD_LOGIC; -- declare the component to be used in this architecture: component add1bit
Port ( cin : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
cout : out STD_LOGIC;
sum : out STD_LOGIC);
end component;
begin -- Instantiate 1-bit adder four times and interconnect:
stage0: add1bit port map(cin,x(0),y(0),c1,s(0));
stage1: ( FILL IN PRELAB )
stage2: (FILL IN PRELAB )
stage3: ( FILL IN PRELAB )
end Structure;
Explanation / Answer
ANSWER:
Library IEEE;
Use IEEE.std-logic-1164.all;
Entity RCA is
Port (a,b: in std-logic-vector(3 down to 0);
Cout: out std-logic;
Sum: out std-logic-vector(3 down to 0);
End entity RCA;
Architechere struct-RCA of RCA
Signal cin: std-logic-vector (3 down to 0);
Component FA is
Port (a,b: in std-logic;
Cin: in std-logic;
Cout: out std-logic;
Sum:out std-logic;
End component;
Begin
Cin (0)=0;
FAO: FA port map(a(0),b(0),cin(0),cin(1)sum(0));
FA1: FA port map(a(1),b(1),cin(1),cin(2)sum(1));
FA2: FA port map(a(2),b(2),cin(2),cin(3)sum(2));
FA3: FA port map(a(3),b(3),cin(3),cout, sum(3));
End architechure street-RCA;
Full adder component :
Library IEEE;
Use IEEE.std-logic-1164.all;
Entity FA i
Port(a,b,cin: in std-logic);
Cout,sum: out std-logic);
End entity FA;
Architechure df-FA of FA is
Begin
Cout<=(a and b)or(b and C)or(a and c);
Sum<=a xor b xor cin;
End architecture df-FA;
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