and this is the relevant figure a. add Rd, Rs, Rt Interpretation RegiRdl RegRs+R

Question

and this is the relevant figure

a. add Rd, Rs, Rt Interpretation RegiRdl RegRs+RegRe | Reglul = Meml ReglRsHffs I 1. What are the values of control signals generated by the control in Figure 4.17 for instruction a &b;? 2 Which resources (blocks) perform a useful function for this instruction? .3 Which resources (blocks) produce outputs, but their outputs are not used for instruction a & b? Which esources produce no outputs for instruction a & b? In this exercise, we examine how resource hazards, control hazards, and ISA design can affeet pipelined

Explanation / Answer

(1)Control Signals :

(2)PC,Instruction memory,Add(PC+4),MUX following Add(ALU result),Control,ALU Control are performed for every type of instruction.Now we'll mention the function specific to the following instructions:

(a)The instruction address is fetched from the PC, then the operands are fetched from the instruction memory, ALU performs the operation, and the result is written to register bank.

For Add,RegDst MUX select the W-Reg to write the result back to register Rd.ALUsrc MUX select read data 2 for ALU,and ALU performs the operation.MemRead,MemWrite is 0.So,ALU result will be written back to register.

(b)The instruction address is fetched from the PC, then the operands are fetched from the instruction memory, ALU performs the operation, memory address is calculated from the data memory, and the result is written to register bank.

For lw,all the blocks gor add will be performed here.Apart from that SignExtend will pad the memory address which is gotten from instruction.MemR is 1 so,memory will be read,MemtoReg is 1 and RegW is 1.So,data will be written back to register from register Rt.

(3)

(a)Branch Add was generated but not used because of the AND operation.For the branch type of instructions this AND will generate 1 then branch will be taken.

And data memory does not produce any output.It will only for load and store type instructions.

(b)Read registers 2,Branch Add are the resources that produce output but is not used. these are not used for the lw instruction,as the ALU result is not written back to the register bank, and read register 2 is not required. ALU result is used to calculate data memory address.

All blocks produce output for lw instructions.

RegDst ALUsrc MtoReg RegW MemR MemW Branch ALUop1 Aluop2 add Rd,Rs,Rt 1 0 0 1 0 0 0 1 0 lw Rt,Offs(Rs) 0 1 1 1 1 0 0 0 0

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