Problem 2: (50%) This problem consists of two questions Q1 and Q2 and considers

Question

Problem 2: (50%) This problem consists of two questions Q1 and Q2 and considers the basic MIPS 5-stage pipeline (F, D, EX, M, WB). (For this problem, you should assume that there is full forwarding.) Q1 Show how the instructions below proceed through the pipeline and indicate how many pipeline stall cycles occur. You should assume the beg instruction is taken. Use (30 marks) 1 23 456 78910 11 12 13 14 15 the following chart (extend the number of columns if needed) add $t1, $s0, $t1l lw t2, (St1) addi $s1, $s1,1 slti St3, St2, 50 beq $t3, 1, iF addi $s2, $s2, 1 j loop F: addi s3, $s3, 1 Q2 Assume the following sequence of instructions is executed in a traditional 5-stage pipeline. Does the lwladd instruction combination represent a data hazard? If so, why? If not, why not? (20 marks) $5, 4 ($6) add $6, $5, $10 sub 7, $6, s5

Explanation / Answer

*

3 STALL

Q2--------------

ADD – Add (with overflow)

Description:

Adds two registers and stores the result in a register

Operation:

$d = $s + $t; advance_pc (4);

Syntax:

add $d, $s, $t

Encoding:

0000 00ss ssst tttt dddd d000 0010 0000

LW -- Load word

Description:

A word is loaded into a register from the specified address.

Operation:

$t = MEM[$s + offset]; advance_pc (4);

Syntax:

lw $t, offset($s)

Encoding:

1000 11ss ssst tttt iiii iiii iiii iiii

lw/add instruction represent data hazard bacuse load instruction first fetch and than decode and than execute or pass value and than available to use.so one cycle stall produce.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 add $t1,s0,t1 F D EX M WB lw $t2,($t1) * F D EX M WB addi $s1,$s1,1 F D EX M WB slti $t3,$t2,50 F D EX M WB beq $t3,1,F

*

* F D EX M WB addi $s2,$s2,1 F D EX M WB j loop F:addi s3,s3,1 F D EX M WB

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