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7.37 A set of parity-check equations for a distance-4 Hamming code with 64 data

ID: 3723570 • Letter: 7

Question

7.37 A set of parity-check equations for a distance-4 Hamming code with 64 data bits and eight parity-check bits are specified by the eight 72-bit constants below, each representing one row the parity-check matrix: c[1]-72 'h80000000000000007f; 72 'h400000003fffffff80 C[3] = 72 'h2 0 0 0 1 f f fc 0 0 07 f f f 80 ; 72'h100fe03fc071807f80 C[5] = 72'h0871e3c3c7878787BE; 72 'h04b66cccd9999999b3; C[7] = 72 ' h02dabS 5 56 aaaaaaadS ; C[2] C[4] C[6] C[8] = = = = Assuming that bits are numbered DI 71:0], bits DI71:64] are the check bits, and DI63:01 are the data bits. Based on these parity-check equations, write a Verilog model Vrhamenc64 for a Hamming encoder with 64-bit data inputs DI[63:0] and a 72-bit encoded data output Do[71:0]

Explanation / Answer

hamming_encode.v

module hamm_enc(out,in,reset);
parameter n=11,k=7;
output [n-1:0] out;
input [k-1:0] in;
input reset;
reg [n-1:0] out;
integer i,j;
always @(in or reset)
begin

if(reset)   
out = 0;  
else begin i=0; j=0;   
while((i<n) || (j<k))   
begin
while(i==0 || i==1 || i==3 || i==7)   
begin  
out[i] = 0;  
i=i+1;
endout[i] = in[j];
i=i+1;

j=j+1;   
end   
if(^(out & 11’b101_0101_0101))   
out[0] = ~out[0];   
if(^(out & 11’b110_0110_0110))
out[1] = ~out[1];   

if(^(out & 11’b000_0111_1000)) out[3] = ~out[3];   
if(^(out & 11’b111_1000_0000)) out[7] = ~out[7];  
end
end
endmodule


hamming_decode.v

module hamm_dec(out,in,reset);
parameter n=11,k=7;
output [k-1:0] out;
input [n-1:0] in;
input reset;
reg [k-1:0] out;
reg r1,r2,r4,r8;
reg [3:0] r;
reg [n-1:0] IN;
integer i,j;
always @(in or reset)
begin  
if(reset)   
out=0;  
else  
begin   
r1 = ^(in & 11’b101_0101_0101);   
r2 = ^(in & 11’b110_0110_0110);   
r4 = ^(in & 11’b000_0111_1000);   
r8 = ^(in & 11’b111_1000_0000);   
r = {r8,r4,r2,r1};   
IN = in;   
IN[r-1] = ~IN[r-1];   
i=0; j=0;   
while((i<n) || (j<k))   
begin
while(i==0 || i==1 || i==3 || i==7)
i=i+1;
out[j]=IN[i];
i=i+1;
j=j+1;   
end
end
endmodule

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