7. [50 points] The following two figures show the format of an x64 (64-bit super

Question

7. [50 points] The following two figures show the format of an x64 (64-bit superset of the x86 architecture supported by AMD and Intel) virtual address, and the format of an x64 page table entry Page map vel Page directory Page table Page table entry Byte within selector 4 selector inter selector selector 9 bits 9 bits 9 bits 9 bits 12 bits 63 62 52 51 32 Physical-Page Base Address This is an architectural limit. A given implementation may support fewer bils.) Reserved, MBZ Physical-Page Base Address a. What is the page size of this architecture? b. Can you think of reasons why current implementations of the x86 architecture limit the number of bits to 48 (=12+9+9+9+9)? c. What is the total size of each table (page map table, page directory table, page table selector table, page table)? d. What are the advantages of a multi-level page table approach?

Explanation / Answer

1. The default page estimate is settled by what the MMU (memory administration unit) of the CPU underpins. In 32-bit secured mode x86 bolsters two sorts of pages:

typical ones, 4 KiB

enormous ones, 4 MiB

Not all x86 processors bolster vast pages. One needs a CPU with Page Size Extension (PSE) abilities. This prohibits pre-Pentium processors. For all intents and purposes all present age x86 CPUs executes it.

4 KiB is broadly popuplar page granularity in different designs as well. One could contend that this size originates from the division of a 32-bit virutal address into two 10-bit records in page registries/tables and the rest of the 12 bits give the 4 KiB page estimate.

4. Advantages and Disadvantages

Advantages:

1. Designating memory is simple and modest

2. Any free page is alright, OS can remove initial one from show it keeps

3. Kills outer fracture

4. Information (page outlines) can be scattered all finished PM

5. Pages are mapped fittingly at any rate

6. Permits request paging and prepaging

7. More proficient swapping

8. No requirement for contemplations about fracture

9. Simply swap out page most drastically averse to be utilized

Disadvantages:

1. Longer memory get to times (page table query)

2. Can be enhanced utilizing TLB

3. Watched page tables

4. Upset page tables

5. Memory necessities (one section for each VM page)

6. Enhance utilizing Multilevel page tables and variable page sizes (super-pages)

7. Watched page tables

8. Page Table Length Register (PTLR) to confine virtual memory measure

9. Interior fracture

Please post the other qustions as another question

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