Problem A . Assuming that there is no structure hazard in the parallel execution

Question

Problem A. Assuming that there is no structure hazard in the parallel execution of two different stages, please identify (1) the type of hazard (Structure hazard, Data hazard, or Control hazard) and (2) in which stage of the 2nd instruction such hazard occurs in the pipelined implementation of two instructions.

(b)

LDR R1, [R3, R6]

;it’s executed in five stages: IF, ID, EX, MEM, WB

SUB R4, R8, #5

;it’s executed in four stages: IF, ID, EX, WB, there is only one “Registers” block

(b)

LDR R1, [R3, R6]

;it’s executed in five stages: IF, ID, EX, MEM, WB

SUB R4, R8, #5

;it’s executed in four stages: IF, ID, EX, WB, there is only one “Registers” block

Explanation / Answer

(1)There is structural hazard between two instructions as both try to do register write(WB) in same clock cycle and there is one register block.

There is no data hazard or control hazard

(2) In WB stage of second instruction structural hazard occurs.

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