Problem A . Assuming that there is no structure hazard in the parallel execution

Question

Problem A. Assuming that there is no structure hazard in the parallel execution of two different stages, please identify (1) the type of hazard (Structure hazard, Data hazard, or Control hazard) and (2) in which stage of the 2nd instruction such hazard occurs in the pipelined implementation of two instructions.

(a) LOOP ……

                  BNE LOOP        ;it’s executed in 3 stages: IF, ID, EX, CPU knows whether “NE” is true at the end of EX

    ORR R7, R9, #5

;it’s executed in four stages: IF, ID, EX, WB

    ORR R7, R9, #5

;it’s executed in four stages: IF, ID, EX, WB

Explanation / Answer

(1)There is control hazard between two instructions as first instruction is a branch instruction and second instruction can only enter into pipeline if previous branch is untaken.

There is no data hazard or structural hazard.

(2) In ID stage of second instruction control hazard occurs.

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