. Consider a CPU that implements two parallel fetch-execute pipelines for supers

Question

. Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle shown below:

·        a one clock cycle fetch

·        a one clock cycle decode

·        a two clock cycle execute

and a 80 instruction sequence:

Show your work. Be sure to factor in the cycles necessary for each instruction to execute.

a)         No pipelining would require _____ clock cycles:

b).       A scalar pipeline would require _____ clock cycles:

c)       A superscalar pipeline with two parallel units would require ______ clock cycles

Explanation / Answer

Ans :

(a)

Calculate the no pipelining :

50*(1+2+3) = 300 clock cycle

Hence clock cycles required at no pipelining is 300 .

(b)

Calculate the scalar pipeline

1+2+(50*3) = 153 clock cycle

Hence clock cycles required at scalar pipelining is 153 .

(c)

Calculate the superscalar pipelining :

1+2+(50/2)*3 = 78 clock cycles

Hence clock cycles required at superscalar pipelining with two parallel units is 78 .

Related Questions

Navigate

• Browse (All)
• Browse #
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.