Verilog program help. Based on the verilog module above. Use the following Test
ID: 3701764 • Letter: V
Question
Verilog program help.
Based on the verilog module above. Use the following Test cases. Calculate Output values for Cout and S_8. Then write a test script and see if the values you have calculated match your simulation results:
Inputs
Outputs
Test Case
Cin
A_8
B_8
Cout
S_8
0
0
12
34
1
0
55
AA
2
0
72
27
3
0
80
08
4
1
12
34
5
1
55
AA
6
1
72
27
7
1
80
08
When interpreting the simulation results it is more convenient work with hexadecimal for evaluating multi-bit quantities. Initially test results are shown in binary
Inputs
Outputs
Test Case
Cin
A_8
B_8
Cout
S_8
0
0
12
34
1
0
55
AA
2
0
72
27
3
0
80
08
4
1
12
34
5
1
55
AA
6
1
72
27
7
1
80
08
ISE Project Navigator (P.20131013) _ CAUsersUSERDocumentsXilinxPrjCECS225LabsLab2-RCA8Lab2-RCA8xíse-RCA8.v] File Edit View Project Source Process Tools Window Layout Help ? | Design 1 ?time 3 cale Ins / 1p3 Simula E 3 module RCA8 (A 8, B 8, Cin, Cout, S 8 Hierarc input 17:0] A 8, B_8: input output output [7:0] S 8: Cin; Cout 7 fa0 FullAdder (FullAd fal FullAdder (FullAd wire co 1, c1 2, c2 3, c3 4, c4 5, c5 6, c6 7: ?Dfa2 _ FullAdder (FullAd? 10 fa3 - FullAdder (FulIA fa4 - FullAdder (FulIA fa5 - FullAdder (FullAd fa6- FullAdder (FullAd 14 fa7 - FullAdder (FullAd FullAdder fao .FA A(A 8[O], 12 13 15 16 .CinCin .FA S S80] .Cout CO1 No Processes Running 18 19 20 21 FullAdder fal( .FA A(A 8[1], Processes: RCA8 .FA B B 81, .Cin ( .FA S S 81 , .Cout cl 2 RA ? Design Summary/Reports Design Utilities User Constraints co 1 23 2 4 25 2 6 27 28 29 30 Synthesize - XST Implement Design Generate Programming. Configure Target Device ? FullAdder fa2( .FA A(A 8[2]), .FA BB 8 2 ), .Cin ( .FA S S8[2] .Cout C23 CAalyze Design Using C.. c1 2 StartDesign Files ? Design Summary (out of date) RCA8.v FullAdder.v RCA8 Tester.v Console INFO: ProjectMgmt - Parsing design hierarchy completed successfully x) INFO : HDLCompiler: 1845 Analyzing Verilog file "c:/Users/USER/Documents/XilinxProj /CECS225Labs/Lab2_RCA8/RCA8.r" into library work - INFO: ProjectMgmt - Parsing design hierarchy completed successfully. ConsoleErrorsWarningsFind in Files Results Ln 10 Col 1 VerilogExplanation / Answer
module fulladder (
input A,
input B,
input Cin,
output Sum,
output Cout
);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule
module fulladder_8bit (
input [7:0] A,
input [7:0] B,
input Cin,
output [7:0] Sum,
output Cout
);
wire w1, w2, w3, w4, w5, w6, w7, w8;
fulladder m0 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(w1));
fulladder m1 (.A(A[1]), .B(B[1]), .Cin(w1), .Sum(Sum[1]), .Cout(w2));
fulladder m2 (.A(A[2]), .B(B[2]), .Cin(w2), .Sum(Sum[2]), .Cout(w3));
fulladder m3 (.A(A[3]), .B(B[3]), .Cin(w3), .Sum(Sum[3]), .Cout(w4));
fulladder m4 (.A(A[4]), .B(B[4]), .Cin(w4), .Sum(Sum[4]), .Cout(w5));
fulladder m5 (.A(A[5]), .B(B[5]), .Cin(w5), .Sum(Sum[5]), .Cout(w6));
fulladder m6 (.A(A[6]), .B(B[6]), .Cin(w6), .Sum(Sum[6]), .Cout(w7));
fulladder m7 (.A(A[7]), .B(B[7]), .Cin(w7), .Sum(Sum[7]), .Cout(w8));
assign Cout = w8;
endmodule
module fulladder_8bit_tb;
reg [7:0] A;
reg [7:0] B;
reg Cin;
wire [7:0] Sum;
integer i, j;
fulladder_8bit adder_4bit(A, B, Cin, Sum, Cout);
initial
begin
$monitor("A = %h, B = %h Cin = %d, Sum = %h, Cout = %d", A, B, Cin, Sum, Cout);
Cin = 1'b0;
repeat(2)begin
A = 8'h12; B = 8'h34; #10;
A = 8'h55; B = 8'hAA; #10;
A = 8'h72; B = 8'h27; #10;
A = 8'h80; B = 8'h08; #10;
Cin = !Cin;
end
end
endmodule
/**************** OUTPUT OF PROGRAM ******************
A = 12, B = 34 Cin = 0, Sum = 46, Cout = 0
A = 55, B = aa Cin = 0, Sum = ff, Cout = 0
A = 72, B = 27 Cin = 0, Sum = 99, Cout = 0
A = 80, B = 08 Cin = 0, Sum = 88, Cout = 0
A = 12, B = 34 Cin = 1, Sum = 47, Cout = 0
A = 55, B = aa Cin = 1, Sum = 00, Cout = 1
A = 72, B = 27 Cin = 1, Sum = 9a, Cout = 0
A = 80, B = 08 Cin = 1, Sum = 89, Cout = 0
A = 80, B = 08 Cin = 0, Sum = 88, Cout = 0
******************************************************/
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