Verilog question 1. Verilog Implementation Write the VERILOG code to implement t
ID: 1716838 • Letter: V
Question
Verilog question
1. Verilog Implementation Write the VERILOG code to implement the following Finite State Machine. This FSM has four states: Sto, Stl, St2, and St3. There are three inputs: Reset, A and B. There is only one output: Q1. A value of x for either of the inputs indicates that it is a "don't care" for that transition. In addition to writing the Verilog code, please also answer the following questions: 1. What is the minimum number of flip-flops needed to implement this FSM? 2. Is this a Mealy or a Moore Machine? A-0, B-x A-0, B x St2 St0 Reset Q1-0 St1 St3 A-1, B-x Q1-0 Q1-1 A-1, B xExplanation / Answer
Please find the verilog code as below:
module BasicFsm (Reset,clk,A,B,Q1);
input Reset;
input clk;
input A;
input B;
output Q1;
reg Q1;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// State Encoding
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
localparam
St0 = 2'b00 ,
St1 = 2'b01 ,
St2 = 2'b10 ,
St3 = 2'b11 ;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// State reg Declarations
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
reg [1:0] state;
reg [1:0] next_state;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
always @ (state or A or B)
begin : FSM_COMBO
case(state)
St0 :
if (A == 1'b0)
next_state = St2;
else if (A==1'b1)
next_state = St1;
St1 :
if (A == 1'b1)
next_state = St3;
else if(A == 1'b0)
next_state = St0;
St2 :
if (A == 1'b1 && B == 1'b1)
next_state = St3;
else if (A == 1'b0)
next_state = St2;
else if (A == 1'b1 && B == 1'b0)
next_state = St1;
St3 :
if (A == 1'b1)
next_state = St3;
else if (A == 1'b0 && B == 1'b1)
next_state = St2;
else if (A == 1'b0 && B == 1'b0)
next_state = St0;
default : next_state = St0;
endcase
end
always @ (posedge clk)
begin : FSM_SEQ
if (Reset == 1'b1)
state <= St0;
else
state <= next_state;
end
always @ (state or Reset)
begin : OUTPUT_LOGIC
if (Reset == 1'b1)
Q1<= 1'b0;
else begin
case(state)
St0 : Q1<= 1'b0;
St1 : Q1<= 1'b0;
St2 : Q1<= 1'b1;
St3 : Q1<= 1'b1;
default: Q1<= 1'b0;
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule
additional question:
1)
number of states = 2n where n is equal to the number of flip flops
here we have 4 states so 22 = 4 so n = 2 = number of flips reqiured to implement the state machine.
so,
number of flips reqiured to implement the state machine is 2
2)
In mealy machine output depend on current state as well as present input and
In moore machine output depends only on current state.
here output depends only on current state so it is a moore machine.
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