Problem 3 15 points Suppose we have a single-cycle datapath implementation (refe

Question

Problem 3 15 points Suppose we have a single-cycle datapath implementation (refer to the previous figure) with the following properties • Reading or writing to instruction or data memory takes 8ns • Reading or writing to register file takes 5ns • ALU operations take 4ns • Assume that all other operations take negligible time a) Calculate how long it takes for a sw instruction to finish (approximately). b) Calculate how long it takes for a lw instruction to finish (approximately). c) Based on these answers, what is the minimum cycle time possible for a single-cycle implementation that can handle both instructions? d) Now suppose use a pipelined datapath with 5 stages (IF, ID, EX, MEM, WB). Assume that the time required for reading/writing to instruction memory, data memory, register file, ALU operations remains unchanged, and the time required for new operations (e.g., reading writing to pipeline registers) is negligible. What should be the minimum cycle time for the five-stage pipelined architecture? Why? e) Calculate how long it takes for a lw and sw instructions to execute (from the time they enter pipeline to the time they leave it).

Explanation / Answer

Ans a)

A store operation copies data from a register into main memory .

In sw instruction first we have to read instruction in order to decode and then reading fron register and then writing into main memory.

so the total time will be - 8+5+8 = 21ns

Ans b) A load operation copies data from main memory into a register.

In lw instruction first we have to read instruction in order to decode and then reading fron main memory and then writing into register.

so the total time will be - 8+8+5 = 21ns

Ans c) Now in single cycle path instruction we can perfrom several operation in serial manner .

Therefore minimum time to complete bath instruction will be 21+21= 42 ns

Ans d) in given question

IF 8ns

ID 8ns

EX 4ns

MEM 8ns

WB 5ns

minimum cycle time for n instruction with the five stage pipelining :- for first instruction all the phases will executed sequentially after that we have to invest maximum time of single phase for all the remaning instruction because all will run parellel

.

= 33 + n * 8

for larger value of n average cycle time will be 8 ns

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