The question is asking to create a calculator using two components, and the code
ID: 3695138 • Letter: T
Question
The question is asking to create a calculator using two components, and the code code for the two components is down. The adder will take 2 four digit binary numbers using 8 switchs. and display the answer on 8 leds. This will be done on a nexus 3 board.
EE 301
Lab#5 Simple calculator (addition only)
In this lab, you will design a simple calculator that does only addition. The calculator adds two 4-bit numbers (A and B) and displays the results on the 8 LEDs. You will use the left four slide switches to enter the value for A and the right four slide switches for the value for B. The calculator also requires three push buttons BTN(2:0) on the FPGA board for the functions “Add”, “AC”, “Reset”. When you press the push button for “Add”, the calculator will display the result of A+B on the LEDs. When you press the push button for “AC”, the calculator will clear the result to zero and all the LEDs will be off. The “Reset” button is to reset the state machine to the initial state. Note that Reset is active high. Figure 1 shows the ASM chart for the calculator. Figure 2 shows the datapath circuit.
Figure
You will need to obtain the ASM chart for the control circuit.
The code for the register component (reg.vhd) is given at the end of this handout. The partial code for the calculator (calc.vhd) is also given. Note that you will need to add the code for the FSM transitions and FSM actions in calc.vhd.
After this, use the provided testbench code (testbench.vhd) and modify it to test the addition function and the AC function. In your simulation, you need to display the state in the waveforms so that you can check it. Then, implement the design and transfer it to the FPGA board. You will need to create a new implementation constraints file to map the signals to the pushbuttons, LEDs, slide switches, and onboard 50Mhz clock. After you have verified the functionality of your circuit, demonstrate your design to the instructor so that he can check it off.
In this lab report, you don’t need to give a write up due to time constraint. Just include: 1) ASM chart for control circuit, 2) VHDL codes reg.vhd and calc.vhd, 3) testbench code, 4) simulation timing diagram
verifying the “Add” and “AC” functions (you must show the state in the waveforms), and 5) implementation constraints file.
Reg.vhd (code for the register component)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg is
Port ( clear : in STD_LOGIC;
load : in STD_LOGIC;
clock: in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end reg;
architecture Behavioral of reg is
begin
process (clock)
begin
if (clock'event and clock='1') then
if clear='1' then
data_out<="00000000";
elsif load='1' then
data_out<=data_in;
end if;
end if;
end process;
end Behavioral;
calc.vhd (main code for calculator)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Calc is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
reg_out: out STD_LOGIC_VECTOR (7 downto 0);
Add : in STD_LOGIC;
reset : in STD_LOGIC;
AC: in std_logic;
clock: in std_logic);
end Calc;
architecture Behavioral of Calc is
type state_type is (s1,s2,s3);
signal y: state_type;
signal A_8bit, B_8bit, sum: std_logic_vector (7 downto 0);
signal clear, load : std_logic;
component reg
Port ( clear : in STD_LOGIC;
load : in STD_LOGIC;
clock: in std_logic;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
-- Part 1: control circuit ---
-- specify state transitions
FSM_transitions: process (reset, clock)
begin
--- **** add code here **** ---
end process;
-- specify action
FSM_actions: process(y)
begin
--- **** add code here **** ---
end process;
-- Part 2: datapath circuit
-- pad A and B to 8 bits
A_8bit <= "0000" & A;
B_8bit <= "0000" & B;
-- adder
sum <= A_8bit + B_8bit;
--register
register1: reg port map( clear, load, clock, sum, reg_out);
end Behavioral;
testbench.vhd (testbench code)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Calc
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
reg_out : OUT std_logic_vector(7 downto 0);
Add : IN std_logic;
reset : IN std_logic;
AC : IN std_logic;
clock : IN std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Add : std_logic := '0';
signal reset : std_logic := '0';
signal AC : std_logic := '0';
signal clock : std_logic := '0';
--Outputs
signal reg_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Calc PORT MAP (
A => A,
B => B,
reg_out => reg_out,
Add => Add,
reset => reset,
AC => AC,
clock => clock
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset<='1';
wait for 40ns;
reset<='0';
***add code here to test the AC and Add.
end process;
END;
rese SI A C S3 SuMS nchange SuMEA A C cle ac Re5ister uA 25 Figurej 1 - ASM chart Figure 2 -Datapath circuitExplanation / Answer
VHDL code to add 4 bit numbers : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binary_4_bit_adder_top is Port ( NUM1 : in STD_LOGIC_VECTOR (4 downto 0) := "00000"; NUM2 : in STD_LOGIC_VECTOR (4 downto 0) := "00000"; SUM : out STD_LOGIC_VECTOR (4 downto 0)); end binary_4_bit_adder_top; architecture Behavioral of binary_4_bit_adder_top is begin SUMRelated Questions
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