Logic design question 3 Please solve a,b,&c If you can help further contact me V

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Logic design question 3 Please solve a,b,&c

If you can help further contact me Vip30003@hotmail.com I'll give a reward for helping 3.[30%] Problems related to memory array design, virtual memory, and cache memory design (a)[1096] An 8-bit microprocessor has a 12-bit address bus. Design a 4 KB memory array using I K x 8 (1 KB) memory chips Each memory chip has two chip selects (CS/ and 2 ) and a R/W input. The microprocessor generates RIW and MITO signals. If you use full decoding indicate the size of the decoder that is used. Clearly show all connections to the memory chips the decoder (if one is used) and the microprocessor (b)[10%] A computer system with a 64K word virtual memory has 32K words of main s of main memory The page size is 4K words. What is the size (in bits) of a virtual memory address? How many bits of a virtual memory address are used for the page displacement (offset or are used for page selection (p)? n)? How many bits # of bits in virtual memory address is # of bits in virtual memory page displacement field is # of bits in virtual memory page selection field is (c)[10%] A microprocessor has a main memory of 32K x 32 and a cache memory of IK x 32 Using direct mapping, what are the sizes of the tag and index fields? # of bits in the tag field is # ofbits in the index field is

Explanation / Answer

A 36 bit address can address 2^36 bytes in a byte addressable machine. Since the size of a page 8K bytes (2^13), the number of addressable pages is 2^36 / >2^13 = 2^23 With 4 byte entries in the page table we can reference 2^32 pages. Since each page is 2^13 B long, the maximum addressable physical memory size is 2^32 * 2^13 = 2^45 B (assuming no protection bits are used).

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