a) Suppose we have a 4-line cache with 16-byte lines, and consider the following

Question

a) Suppose we have a 4-line cache with 16-byte lines, and consider the following sequence of memory addresses accesses. For each row of each column, indicate with an H or M whether that memory access results in a cache hit or a cache miss given the caching scheme for that column. (the first column below is word addressable)

b) Change the access pattern such that allow of the caches exhibit the same miss rate. Write the new pattern on the line below.

Address (words) Fully-Associative (LRU) 2-Way Set Associative (LRU) Direct Mapped 0 4 8 12 16 0 4 8 12

Explanation / Answer

Set Associative Caches

• Basic Idea: a memory block can be mapped to more than one location in the cache

• Cache is divided into sets • Each memory block is mapped to a particular set

• Each set can have more than one block – Number of blocks in set = associativity of cache – If a set has only one block, then it is a direct-mapped cache

• I.e. direct mapped caches have a set associativity of 1 • Each memory block can be placed in any of the blocks of the set to which it maps

B) Answer for b part same pattern of cache but only Hit rate change.Miss rate same as previous answer.

address(words) Fully associative(LRU) 2 way set associative Direct Mapped 0 M M M 4 M M M 8 M M M 12 M M M 16 M M M 0 H H M 4 H M M 8 H M M 12 H M M

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