Slide 111: This exercise is intended to reinforce a good understanding of except

Question

Slide 111:

This exercise is intended to reinforce a good understanding of exceptions. Briefly explain how MIPS is designed to handle exceptions. The slide 111 shows a piece of code used in illustrating exception handling. Use this code and report the contents of the register EPC, and the contents of the Cause register when the handler takes over. What initial address of the handler would be loaded into PC and what would the contents of the PC be if the handler returns control to the interrupted program?

Explanation / Answer

(a)

MIPS or "Microprocessor without Interlocked Pipeline Stages" is a RISC architecture without any hardware interlocks. The MIPS processor used 32 registers, each 32 bits wide. The instruction set of 111 instructions. The instruction set consisted of a variety of basic instructions enlisted as follows:

The instructions are simpler and much less in number when compared to CISC microprocessors. Even the addressing modes are simpler and much less in number when compared to Intel Microprocessors. MIPS CPU, all the arithematic and logical instructions are of register mode of addressing,where the operands reside in the set of 32 bit registers. The load and store instructions are data transfer instructions from the register to memory and vice versa. For such data transfer, Base Dispalcement addressing mode is used,where the effective address is computed by adding the content of register(base) with a displacement provided immediately in the instruction. Many instructions supported by this processor are three address instructions.

MIPS powers many consumer electronic and other devices. It is a licensed architecture used by many chip making companies, video games and countless network boxes. Many networking companies use MIPS, because it is a convenient, clean,and easily scaled architecture around which special purpose network processors or protocol engines can be added.

An exception is an unexpected event from within the processor.When an exception occurs, the hardware begins executing code that performs an action in response to the exception. This action may involve killing a process, outputting a error message, communicating with an external device, or horribly crashing the entire computer system. The instructions responsible for this action reside in the operating system kernel.

(b)

When an exception occurs,the processor may perform the following actions:

EPC <= PC

Cause <= (cause code for event)

Status <= Status << 4

PC <= (handler address)

To overcome this, the following actions to perform:

PC <= EPC

Status <= Status >> 4

(c)

A sequence of instructions start at initial address will check the cause of the exception and will set the address to 00000004(in hex).

Cause Register:

Number   Name   Description
00             INT        External Interrupt
01      IBUS      Instruction bus error
10            OVF       Arithmetic overflow
11      SYSCALL   System call

Status register:

Bit   Exception
3       INT
2      IBUS
1   OVF
0      SYSCALL

Register Set:

Register name   Register number   Usage
Status                  12          Interrupt mask and enable bits
Cause          13       Exception type
EPC       14                      Register containing following address of instruction where exception occurred

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