A bus protocol requires the CPU to put the address on the bus during the first c

Question

A bus protocol requires the CPU to put the address on the bus during the first clock period. On the fourth clock period for every clock period afterwards data is retrieved from the RAM. Assume the system has a 128 bit wide bus. The system always reads 64 bytes at a time. (Note the diagram above may or may not show more or less cycles than necessary.) How many bus clock cycles does it take from when the CPU first requests the data until 64 bytes have been read? If the bus operates at 800 MHz, how long is a single clock cycle? How many nanoseconds does it take to read 64 bytes from the RAM?

Explanation / Answer

1Q.)How many bus clock cycles does it take from when the CPU first requests the data until 32 bytes have been read?

Ans)

64 bits wide / 8 bits/byte = 8 byte wide bus = 8 bytes / cycle

32 bytes / 8 bytes/cycle = 4 cycles + 3 cycles = 7 cycles

2Q).If the bus operates at 500 MHz, how long is a single clock cycle?

Ans)

1 / 500*106 cycles/sec = 2.0*10-9 sec/cycle = 2.0 nanosecond / cycle

3Q).How many nanoseconds does it take to read 32 bytes from the RAM?

Ans)

2.0 nanosec / cycle * 7 cycles = 14.0 nanoseconds

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