Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

1 These registers are set during the execution of an instruction C. Control D. C

ID: 3627338 • Letter: 1

Question



1 These registers are set during the execution of an instruction

C. Control D. Condition code

A. Data registers B.address registers





ANS :



2 This plays a key role during exceptions and procedure calls

A. Segment pointer B. Status register

C. Stack pointer D. None of the above



ANS :



3. The operating system executes certain privileged instructions by setting the

A. Privileged register B. Status Register

C. Supervisor bit D. Stack pointer



ANS :



4. Early microprocessors had an instruction cycle consisting of these stages

A. Fetch, Decode and Execute B. Fetch, Execute, Interrupt

C. Fetch, Decode, Write Back D. All of the above



ANS :



5. The location to store the address of the current instruction during an interrupt cycle is given by,

A. MAR B. Stack pointer

C. MBR D. None of the above



ANS :



6. In pipelining there is a requirement of this between stages

A. Memory B. Registers

C. Buffer D. None of the above



ANS :



7. This stage in a pipeline involves both reading and writing of operands

A. Fetch B. Decode

C. Execution D. Memory Write



ANS :



8.This type of instruction does not need a write back stage

A. Load B. Store

C. Add D. Multiply



ANS :



Explanation / Answer

Dear, 1 These registers are set during the execution of an instruction
C. Control D. Condition code
A. Data registers B.address registers
ANS: A.Data registers
2 This plays a key role during exceptions and procedure calls
A. Segment pointer B. Status register
C. Stack pointer D. None of the above ANS: C. Stack pointer

3. The operating system executes certain privileged instructions by setting the
A. Privileged register B. Status Register
C. Supervisor bit D. Stack pointer
ANS: D. Stack pointer

5. The location to store the address of the current instruction during an interrupt cycle is given by,
A. MAR B. Stack pointer
C. MBR D. None of the above
ANS: A. MAR


7. This stage in a pipeline involves both reading and writing of operands
A. Fetch B. Decode
C. Execution D. Memory Write
ANS: D. Memory Write