This exercise examines the impact of different cache designs, specifically compa

Question

This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3. Using the references from Exercise 5.3, show the final cache contents for a three-way set-associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block offset bits, and if it is a hit or a miss. Using the references from Exercise 5.3, show the final cache contents for a fully associative cache with one-word blocks and a total size of eight words. Use LRU replacement. For each reference identify the index bits, the tag bits, and if it is a hit or a miss. Using the references from Exercise 5.3, what is the miss rate for a fully associative cache with two-word blocks and a total size of eight words, using LRU replacement? What is the miss rate using MRU (most recently used) replacement? Finally what is the best possible miss rale fur this cache, given any replacement policy? Multilevel caching is an important technique to overcome the limited amount of space that a first level cache can provide while still maintaining its speed. Consider a processor with the following parameters: Calculate the CPI for the processor in the table using: only a first-level cache, a second-level direct-mapped cache, and a second-level eight-way set-associative cache. How do these numbers change if main memory access time is doubled? If it is cut in half?

Explanation / Answer

please rate - thanks a. Binary address: 12, 100001102, 110101002, 12, 100001112,110101012, 101000102, 101000012, 102, 1011002, 1010012, 110111012 Tag: Binary address >> 3 bits Index: (Binary address >> 1 bit) mod 4 Hit/Miss: M, M, M, H, H, H, M, M, M, M, M, M Final contents (block addresses): Set 00: 02, 101000002, 1010002 Set 01: 101000102, 102 Set 10: 110101002, 1011002 Set 11: 100001102 b. Binary address: {bits 7–3 tag, 2–1 index, 0 blockoffset} 00000 11 02, Miss 11010 11 02, Miss 10101 11 12, Miss 11010 11 02, Hit 00000 11 02, Hit 01010 10 02, Miss 01000 00 12, Miss 10101 11 02, Hit 01000 00 02, Miss 01101 00 12, Miss 01010 10 12, Hit 11010 11 12 Hit Tag: Binary address >> 3 bits Index(or set#): (Binary address >> 1 bit) mod 4 Final cache contents (_block_addresses, in base 2): set: blocks (3 slots for 2-word blocks per set) 00 : 010000002, 010000002, 011010002 01 : 10 : 010101002 11 : 000001102, 110101102, 101011102 5.8.2 a. Binary address: 12, 100001102, 110101002, 12, 100001112,110101012, 101000102, 101000012, 102, 1011002, 1010012, 110111012 Tag: Binary address Index: None (only one set) Hit/Miss: M, M, M, H, M, M, M, M, M, M, M, M Final contents (block addresses): 100001112, 110101012, 101000102, 101000012, 102, 1011002, 1010012,110111012 b. Binary address: {bits 7–0 tag, no index or blockoffset} 000001102, Miss 110101102, Miss 101011112, Miss 110101102, Hit 000001102, Hit 010101002, Miss 010000012, Miss 101011102, Miss 010000002, Miss 011010012, Miss 010101012, Miss, (LRU discard block 101011112) 110101112, Miss, (LRU discard block 010101002) Tag: Binary address Final cache contents (block addresses): (8 cache slots, 1-word percache slot) 000001102 110101102 010101012 110101112 010000012 101011102 010000002 011010012 010101012 110101112 5.8.3 a. Binary address: 12, 100001102, 110101002, 12, 100001112,110101012, 101000102, 101000012, 102, 1011002, 1010012, 110111012 Hit/Miss, LRU: M, M, M, H, H, H, M, M, M, M, M, M Hit/Miss, MRU: M, M, M, H, H, H, M, M, M, M, M, M Given 2 word blocks, the best miss rate is 9/12. b. Binary address: {bits 7–1 tag, 1 block offset} (8 cache slots, 2-words per cache slot) 0000011 02, Miss 1101011 02, Miss 1010111 12, Miss 1101011 02, Hit 0000011 02, Hit 0101010 02, Miss 0100000 12, Miss 1010111 02, Hit 0100000 02, Hit 0110100 12, Miss 0101010 12, Hit 1101011 12, Hit No need for LRU or MRU replacement policy, hence best miss rate is6/12. 5.8.4 a. Base CPI: 2.0 Memory miss cycles: 125 cycles/(1/3) ns/clock = 375 clockcycles 1. Total CPI: 2.0 + 375 × 5% = 20.75/39.5/11.375(normal/double/half) 2. Total CPI: 2.0 + 15 × 5% + 375 × 3% =14/25.25/8.375 3. Total CPI: 2.0 + 25 × 5% + 375 × 1.8% =10/16.75/6.625 b. Base CPI: 2.0 Memory miss cycles: 100 clock cycles 1. Total CPI = base CPI + memory miss cycles × 1st levelcache miss rate 2. Total CPI = base CPI + memory miss cycles × global missrate w/2nd level direct-mapped cache + 2nd level direct-mapped speed × 1st level cache missrate 3. Total CPI = base CPI + memory miss cycles × global missrate w/2nd level 8-way set assoc cache + 2nd level 8-way set assoc speed × 1st level cachemiss rate 1. Total CPI (using 1st level cache): 2.0 + 100 × 0.04 =6.0 1. Total CPI (using 1st level cache): 2.0 + 200 × 0.04 =10.0 1. Total CPI (using 1st level cache): 2.0 + 50 × 0.04 =4.0 2. Total CPI (using 2nd level direct-mapped cache): 2.0 + 100× 0.04 + 10 × 0.04 = 6.4 2. Total CPI (using 2nd level direct-mapped cache): 2.0 + 200× 0.04 + 10 × 0.04 = 10.4 2. Total CPI (using 2nd level direct-mapped cache): 2.0 + 50× 0.04 + 10 × 0.04 = 4.4 3. Total CPI (using 2nd level 8-way set assoc cache): 2.0 + 100× 0.016 + 20 × 0.04 = 4.4 3. Total CPI (using 2nd level 8-way set assoc cache): 2.0 + 200× 0.016 + 20 × 0.04 = 6.0 3. Total CPI (using 2nd level 8-way set assoc cache): 2.0 + 50× 0.016 + 20 × 0.04 = 3.6

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