a) What will be the logic levels on the external SRC buseswhen each of the given
ID: 3610591 • Letter: A
Question
a) What will be the logic levels on the external SRC buseswhen each of the given SRC instruction is executing on theprocessor? Complete Table: A all numbers are in the decimal numbersystem, unless noted otherwise. (Assume the required missinginformation if necessary)
b) Specify memory addressing modes for each of theSRC instructions given in Table.
SRC
instruction
RTL Equivalent
Address
Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Ld
r3,12(r5)
Ld r2,16
Table A
Assumptions:
• All memory content is aligned properly.
• In other words, all the memory accesses start ataddresses divisible by 4.
• Value in the PC = 000DC348h
Memory map with assumed values
Memory Address
Memory Content
…………
…..
00000020h
D2h
000DC340h
51h
00000021h
96h
000DC341h
CAh
00000022h
49h
000DC343h
D5h
00000023h
2Fh
000DC344h
E2h
………
….
………
……
000DC300h
44h
00AB1240h
O7h
000DC301h
23h
00AB1241h
85h
000DC302h
E3h
00AB1242h
E5h
000DC303h
D5h
00AB1243h
3Dh
Fig. 3
Register map with assumed values
Register Name
Content
R[0]
0012A54Bh
R[1]
10234CB8h
R[2]
D296492Fh
R[3]
001400CDh
R[4]
B7432301h
R[5]
00AB1234h
R[6]
00000020h
R[7]
01432D7Fh
R[8]
00B94821h
R[9]
00CDA7A3h
R[10]
0031A0F0h
R[11]
0012A246h
R[12]
000FAB17h
Fig. 4
SRC
instruction
RTL Equivalent
Address
Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Ld
r3,12(r5)
Ld r2,16
Explanation / Answer
SRC Instruction
RTL Equilent
Address bus<31 0>
Data bus
<31 0>
M(R)
M(W)
LD r3,12(r5)
R[3]<-M[12+R[5]
00AB1240h
0785E530h
1
0
LD r2,16
R[2]<-M[16]
00000020h
D296492fh
1
0
(b) Specify memory addressing modes for each of the SRCinstructions given in Table.
Solution:-
Memory Addressing
SRC Instruction
LD r7,12(r5)
LD r2,16
Addressing Mode
Displacement
Direct
SRC Instruction
RTL Equilent
Address bus<31 0>
Data bus
<31 0>
M(R)
M(W)
LD r3,12(r5)
R[3]<-M[12+R[5]
00AB1240h
0785E530h
1
0
LD r2,16
R[2]<-M[16]
00000020h
D296492fh
1
0
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