Q: Write Comparisons based on the following parametersof Instruction Set Archite
ID: 3610176 • Letter: Q
Question
Q: Write Comparisons based on the following parametersof Instruction Set Architecture between Intel and MIPSarchitecture. [25]
Intel
MIPS
Class of ISA
Memory Addressing and Addressing Modes
Types and Size of Operands
Control Flow instruction
Encoding an ISA
Note:
Q: Write Comparisons based on the following parametersof Instruction Set Architecture between Intel and MIPSarchitecture. [25]
Intel
MIPS
Class of ISA
Memory Addressing and Addressing Modes
Types and Size of Operands
Control Flow instruction
Encoding an ISA
Note:
- Assignment should be in your own wordings not copied from net,handouts or books.
- Your complete assignment should be “to the point”and not more than one page.
Explanation / Answer
Class of ISA ( Instruction Set Architecture)
INTEL :
The complete Intel Architecture instruction set includes theinteger, floating-point, MMX technology, and system instructions.The instruction descriptions are arranged in alphabetical order.For each instruction, the forms are given for each operandcombination, including the opcode, operands required, and adescription. Also given for each instruction are a description ofthe instruction and its operands, an operational description, adescription of the effect of the instructions on flags in theEFLAGS register, and a summary of the exceptions that can begenerated.
MIPS instructions fall into 5 classes:
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Other (exception, register movement to/from GP registers,etc.)
Memory Addressing & Addressing modes :
Intel :
The addressing modes in Intel are,
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
MIPS has 5 ways of addressing data
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Type and size of Operands :
Intel :
In general it supports 16 bit instructions and can be extendableupto 32 bit.
MIPS :
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
Control Flow Instructions :
Intel :
Branch and Jump instructions
MIPS :
BRANCH and JUMP are the control instructions in MIPS
Intel
MIPS
Class of ISA
integer, floating-point, MMX technology, system instructions
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Memory Addressing and Addressing Modes
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Types and Size of Operands
In general it supports 16 bit instructions and can be extendableupto 32 bit.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
Control Flow instruction
Branch and Jump instructions
BRANCH and JUMP are the control instructions in MIPS
Class of ISA ( Instruction Set Architecture)
INTEL :
The complete Intel Architecture instruction set includes theinteger, floating-point, MMX technology, and system instructions.The instruction descriptions are arranged in alphabetical order.For each instruction, the forms are given for each operandcombination, including the opcode, operands required, and adescription. Also given for each instruction are a description ofthe instruction and its operands, an operational description, adescription of the effect of the instructions on flags in theEFLAGS register, and a summary of the exceptions that can begenerated.
MIPS instructions fall into 5 classes:
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Other (exception, register movement to/from GP registers,etc.)
Memory Addressing & Addressing modes :
Intel :
The addressing modes in Intel are,
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
MIPS has 5 ways of addressing data
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Type and size of Operands :
Intel :
In general it supports 16 bit instructions and can be extendableupto 32 bit.
MIPS :
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
Control Flow Instructions :
Intel :
Branch and Jump instructions
MIPS :
BRANCH and JUMP are the control instructions in MIPS
please rate as lifesaver regards.
Class of ISA ( Instruction Set Architecture)
INTEL :
The complete Intel Architecture instruction set includes theinteger, floating-point, MMX technology, and system instructions.The instruction descriptions are arranged in alphabetical order.For each instruction, the forms are given for each operandcombination, including the opcode, operands required, and adescription. Also given for each instruction are a description ofthe instruction and its operands, an operational description, adescription of the effect of the instructions on flags in theEFLAGS register, and a summary of the exceptions that can begenerated.
MIPS instructions fall into 5 classes:
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Other (exception, register movement to/from GP registers,etc.)
Memory Addressing & Addressing modes :
Intel :
The addressing modes in Intel are,
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
MIPS has 5 ways of addressing data
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Type and size of Operands :
Intel :
In general it supports 16 bit instructions and can be extendableupto 32 bit.
MIPS :
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
Control Flow Instructions :
Intel :
Branch and Jump instructions
MIPS :
BRANCH and JUMP are the control instructions in MIPS
Intel
MIPS
Class of ISA
integer, floating-point, MMX technology, system instructions
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Memory Addressing and Addressing Modes
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Types and Size of Operands
In general it supports 16 bit instructions and can be extendableupto 32 bit.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
Control Flow instruction
Branch and Jump instructions
BRANCH and JUMP are the control instructions in MIPS
Class of ISA ( Instruction Set Architecture)
INTEL :
The complete Intel Architecture instruction set includes theinteger, floating-point, MMX technology, and system instructions.The instruction descriptions are arranged in alphabetical order.For each instruction, the forms are given for each operandcombination, including the opcode, operands required, and adescription. Also given for each instruction are a description ofthe instruction and its operands, an operational description, adescription of the effect of the instructions on flags in theEFLAGS register, and a summary of the exceptions that can begenerated.
MIPS instructions fall into 5 classes:
Arithmetic/logical/shift/comparison
Control instructions (branch and jump)
Load/store
Other (exception, register movement to/from GP registers,etc.)
Memory Addressing & Addressing modes :
Intel :
The addressing modes in Intel are,
Immediate addressing mode
Register addressing
Direct addressing
Indirect addressing
Indexed
MIPS has 5 ways of addressing data
Immediate: data is in instruction itself
Register: register number in instruction tells which registercontains data
Base/offset: offset value added to base register
PC-relative: offset added to PC
Pseudo direct: offset from instruction merged with PC
Type and size of Operands :
Intel :
In general it supports 16 bit instructions and can be extendableupto 32 bit.
MIPS :
The type of operands that it can handle are bit string,character, decimal, integers and floating point numbers.
The size of operands in Intel are 8-bit, 16-bit, 32-bit integersand 32-bit and 64-bit IEEE 754 floating-point.
Control Flow Instructions :
Intel :
Branch and Jump instructions
MIPS :
BRANCH and JUMP are the control instructions in MIPS
please rate as lifesaver regards.
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