25.A new instruction, SMR (Store Multiple Registers), with symbolic opcode name
ID: 3606420 • Letter: 2
Question
25.A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple-cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] species the address in memory M to which the rst register R[SB] is to be stored. The registers to be stored are R[SB], R [(SB + 1) modulo 8], ..., R [(SB + 7) modulo 8] in Memory M Addresses R[SA], R[SA] + 1, ..., R[SA] + 7. Design this instruction presenting your nal results in the form shown in Table 15.
26.A new instruction LMR (Load Multiple Registers), with symbolic opcode name LMR, is to be implemented for the multiple-cycle computer. The instruction is to retrieve the register contents stored by use of SMR in Problem 25 from memory M and place it in the eight registers. Assume that R[SA] and SB have same values as for SMR for such a retrieval. Design this instruction presenting your nal results in the form shown in Table 15. this questions from logic and computer design fundamentals book edition 4
Explanation / Answer
Multiple register transfer instructions provide an efficient way of moving the contents of many registers to and from memory.
Advantages:
The transfer addresses are determined by the contents of the base register,Rn. The Load and Store multiple register instructions allow between 1 and 16 registers to be transferred to/from the memory.The registers are transferred in the order of lowest to highest. The lowest register gets transferred to/from the lowest memory address. Rn would have a initial value of 0x1000 unless it was also in the transfer list of a LMR instruction.
Base register is used to determine where memory access should occur.
Here the base register is R[SA] and it can be automatically updated following the transfer of R[SB] by appending it with an '!'. In other words R[SA]!=R[SA]+1(automatically updated)
A stack is an area of memory which increments as new data is pushed on to the top of it and decrements when data is popped off the top. The purpose of using stack is to create temperory register workplace for subroutines. Any registers can be pushed at the start of subroutine and popped off again at the end to store them before return to the caller.
1) SMRIA R[SA]!, {R[SB], ..R[(SB+7)]modulo 8}
SMR:Store multiple registers. To implement this stack operation the SMR/LMR instruction should be specified exactly what functionality the instruction is going to perform: that is to specify increment/decrement the base pointer, before or after the memory access
SMRIA/LMRIA: Increment after
SMRIB/LMRIB: Increment before
SMRDA/LMRDA: Decrement after
SMRDB/LMRDB: Decrement Before
Here we are going to increment the base pointer R[SA] to store the contents of registers R[SB] to R[(SB+7)modulo 8]. So we are using SMRIA/LMRIA instruction
2)LMRIA R[SA]!, {R[SB],...R(SB+7)modulo 8}
R[SB] is the pointer to first block from where the content is retrieved and loaded in R[SA]
R(SB+7)modulo 8 is the last block retrieved and stored in R[SA]+7
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