20. [10] A new instruction is to be added to the MIPS instruction set. Assembly

ID: 3600351 • Letter: 2

Question

20. [10] A new instruction is to be added to the MIPS instruction set. Assembly Language Instruction: Instruction Type: Description addmí Rt, Rs, Immediate This instruction adds the contents of the memory location pointed to by register Rs, to the sign-extended immediate value, and stores the result in register Rt. RTL description : RF[Rt] M[ RF[Rs] ] + Sign Ext[Immediate] Specify the micro-operations needed to implement this instruction on the One bus implementation of the MIPS processor. In addition, specify the control signals that must be asserted for each micro-operation. Use RTL to specify the micro-operations. Assume that the instruction has been fetched and is in the I

Explanation / Answer

I-type is short for "immediate type". The format of an I-type instuction looks like:

B31-26

B25-21

B20-16

B15-0

opcode

register s

register t

immediate

The I-type instruction looks like:

add rt, rs, immed

In this case, rt is the destination register, and rs is the only source register. It is unusual that rd is not used, and that rd does not appear in bit positions B25-21 for I-type instruction.

The semantics of the addi instruction are;

R[t] = R[s] + (IR15)16 IR15-0

where IR refers to the instruction register, the register where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value.

Basically, the semantics says to sign-extend the immediate value to 32 bits, add it (using signed addition) to register R[s], and store the result in register rt.

RTL Instruction:

As instruction is already in IR So it only needs be decoded, transferred and then addition is to be done.

Then result is transferred to Rt.

Decode:

D0,D1,D2,…,D7 <--Decode IR(12-14)

AR <-- IR (0-11), I <-- IR(15)

Transfer from register Rs to memory

M[AR],Rs

Data is transferred to Data register

DR <-- M[AR]

Addition:

AC <-- DR + IR15,

Transfer from AC to Rt

Rt <-- AC