DFF component is written below. LIBRARY IEEE; USE ieee.std_logic_1164.ALL; USE i
ID: 3599394 • Letter: D
Question
DFF component is written below.
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY HW7 IS
PORT (clk,reset_n,d : IN std_logic; --reset_n = low active
q: OUT std_logic);
END ENTITY HW7;
ARCHITECTURE Behavioral OF HW7 IS --DFF with a synchronous reset
BEGIN
PROCESS (CLK)
BEGIN
IF (rising_edge(clk)) THEN
IF(reset_n = '0') THEN
q <= '0' ;
ELSE
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE Behavioral;
5. Create a JKFF from a DFF and additional logic. Start with one of the DFFs from Question 4 as a component and build other logic around it to implement the following truth table. Submit your code. 0 0 No change 0 0 Logic CLK RESETNExplanation / Answer
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY HW7 IS
PORT (clk,reset_n,d : IN std_logic; --reset_n = low active
q: OUT std_logic);
END ENTITY HW7;
ARCHITECTURE Behavioral OF HW7 IS --DFF with a synchronous reset
BEGIN
PROCESS (CLK)
BEGIN
IF (rising_edge(clk)) THEN
IF(reset_n = '0') THEN
q <= '0' ;
ELSE
q <= d;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE Behavioral;
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