Realize Verilog code to multiply an 8-bit input called ‘data’ by a fixed constan

Question

Realize Verilog code to multiply an 8-bit input called ‘data’ by a fixed constant, 11 and 15 respectively in decimal. Complete the following Verilog code, write a test bench

module multiply (data, product_11, product_15);

input [7:0] data ;

output [11:0] product_11 ;

output [11:0] product_15 ;

wire [11:0] product_11 ;

wire [11:0] product_15 ;

assign product_11 = ____________________; // 8 x data + 2 x data + data

assign product_15 = ____________________; // 8 x data + 4 x data + 2 x data + data

endmodule

Question 1: Realize Verilog code to multiply an 8-bit input called 'data' by a fixed constant, 11 and 15 respectively in decimal. Complete the following Verilog code, write a test bench, and include your simulation results. module multiply (data, product_11, product 15); input [7:0] data output [11:0] product_11; output [11:0] product_15 wire [11:0] product_11; wire [11:0] product_15; assign product_- assign product_15- endmodule //8 x data 2 x data +data //8 x data +4 x data +2 x data data

Explanation / Answer

Multiplication on binary number is simply a shift operation. Multiplying by 2 shifts the bits 1 position left.

Multiplying with 4 shifts the bits 2 positions left. Multiplying by 8 shifts the bits 3 positions left.

Similary division also uses shifting operation. Dividing by 2 shift the bits 1 position right.

Dividing with 4 shifts the bits 2 positions right. Dividing with 8 shifts the bits 3 positions right.

In this multiplying the data by 11 can be divided as 8 * data + 2 * data + data

and multiplying the data by 15 can be divides as 8 * data + 4 * data + 2 * data + data

In this way any multiplicatins can be sub divided into sum of multiplications and apply shift operators, similarly for division.

So the verilog is as follows :

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module multiply( data, product_11, product_15 );

input [ 7 : 0 ] data;;

output [ 11 : 0 ] product_11;

output [ 11 : 0 ] product_15;

wire [ 11 : 0 ] product_11;

wire [ 11 : 0 ] product_15;

assign product_11 = data << 3 + data << 1 + data; // << 3 makes multiply by 8, << 1 makes multiply by 2

assign product_15 = data << 3 + data << 2 + data << 1 + data;// << 3 makes multiply by 8, <<2 makes multiply by 4 //<< 1 makes multiply by 2

endmodule;

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