5. [30 pts, 5 pts eachl Suppose you add registers to the 16-bit prefix adder as

Question

5. [30 pts, 5 pts eachl Suppose you add registers to the 16-bit prefix adder as shown in the figure below (registers indicated by blue rectangles) (a) What is the minimum cycle time (Tc) of the system? (b) What is the fastest frequency at which you can run the system? (c) How long does it take to complete a single calculation (i.e., S = A + B)? (i.e., What is the latency?) (d) After the first calculation completes, how often is a result produced? How many calculations per second occur after the first calculation completes? (i.e., What is the throughput?) (e) Compare the latency and throughput of the prefix adder from Exercise 4 and this one. 15 14 1312 11 10 9 87 6 5 4 3 2 01 14:13 10:9 8:7 6:5 4:3 0:-1 10:7 9:7 6:3 5:3 14:7 13:7 12:711:7 14:-1 13-1 12:-1 11:-1 10:-1 9-18-1 7:-1 15 14 1312 10 9 8765 4 320 0 Legend 1:J A, B G-1 1A, B, P G i:j

Explanation / Answer

consider the 16 bit prefix adders, (blue rectangles), middle circuit in the below.

first step is to calculate, the delay in the longest path.

delay 1 = tpd of AND gate + tpd of OR gate = 200ps + 200ps= 400 ps

now consider the clk timing of register (flip flop):

delay 2 = FF ack time+ setup time+ hold time = 120ps+75ps + 110ps = 305 ps

total delay = 400+305 = 705 ps

fastest frequency = 1/ total delay = 1/705ps = 1418439716.31 Hz = 1418.439 MHz

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