The following is the VHDL code of a different counter with JK flip-flops. Modify
ID: 3575006 • Letter: T
Question
The following is the VHDL code of a different counter with JK flip-flops. Modify it so as to correspond to your design.
---------------------------------------------------------------
-- < put your name here >
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library ieee ;
use ieee.std_logic_1164.all;
entity counter is
port( clear,clock: in std_logic;
Q: out std_logic_vector(3 downto 0));
end counter;
-----------------------------------------------------------------
architecture cct of counter is
signal S: std_logic_vector(3 downto 0):="0000"; -- initialize
signal J,K: std_logic_vector (3 downto 0);
begin
-- 1) The combinational part
J(3) <= S(2) and S(1) and S(0);
K(3) <= S(3) and S(0);
J(2) <= S(1)and S(0);
K(2) <= S(1) and S(0);
J(1) <= not S(3) and S(0);
K(1) <= not S(3) and S(0);
J(0) <= '1' ;
k(0) <= '1' ;
-- 2) The flip-flop part
process(clear, clock)
begin
if clear='0' then S <= "0000";
elsif falling_edge(clock) then
S(3 downto 0) <= (J(3 downto 0) and not S(3 downto 0)) or (not K(3 downto 0) and S(3 downto 0));
end if;
end process;
Q <= S ;
end cct;
1. Enter the simulation commands that correspond the following:
The clock pulse is repeated each 20ns. Set clear=0. At 100ns, it becomes 1.
Run for 600ns
2. Put an image copy of the Timing Diagram showing only: clock, clear & flip-flop output (the Qs).
3. Indicate if the Timing Diagram is as expected.
fast plz
Explanation / Answer
to run the simulator for 600ns, enter:
VSIM > run 600
process (clear, clock)
begin
clk<= not(clk) after 10ns;
if clk = 100ns then clear = 0;
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