PLEASE I NEED SOME HELP IN THIS PROBLEM OF VHDL - DIGITAL LOGIC DESIGN - please

Question

PLEASE I NEED SOME HELP IN THIS PROBLEM OF VHDL - DIGITAL LOGIC DESIGN - please explain you answer and will graded will not grade if you left a comment or emails , thank you

I. Write a small function which receives an integer and returns a nibble (4 bits) indicating if the integer is (overflow, sign, parity, zero). An overflow is any number larger than 65535, which is 2 bytes (or 16 bits). The integer is 32 bits long so it can hold larger numbers.

function findFlags(number : integer) returns std_logic_vector is

--place your code and required variables here

--you may assume the existence of the following data type:

-- type NIBBLE is array (3 downto 0) of std_ulogic;

end function

Explanation / Answer

function findFlags(number : integer) return std_logic_vector is
   variable my_Data:std_logic_vector(31 downto 0);
   variable flag_reg:std_logic_vector(3 downto 0):="0000";      
   begin
       --------------DATA CONVERSION FROM INTEGER TO 32 BIT STD_LOGIC_VECTOR--------------      
       my_Data := std_logic_vector(to_unsigned(number, my_Data'length));
       -----------------CHECK FOR OVERFLOW BIT -------------------------------------------
       for i in 16 to 31 loop
           flag_reg(3):=my_Data(i) or flag_reg(3);  
       end Loop;                       
       -----------------CHECK FOR SIGN BIT -----------------------------------------------
       if(my_Data(15)='1') then
           flag_reg(2):='1';  
       end if;
       -----------------CHECK FOR PARITY BIT -----------------------------------------------
       for i in 0 to 31 loop
           flag_reg(1):=my_Data(i) xor flag_reg(1);  
       end Loop;               
       -----------------CHECK FOR ZERO BIT -----------------------------------------------
       if(number=0) then
           flag_reg(0):='1';  
       end if;              
   return flag_reg;
      
     end function;

-----------------------------TESTING PROGRAM --------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.My_Operation.All;
entity Check_Flag is
   PORT(DATA_INPUT:IN integer;
         DATA_OUTPUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end Check_Flag;
architecture OP1 of Check_Flag is
begin
   PROCESS(DATA_INPUT)
   BEGIN
       DATA_OUTPUT<=findFlags(DATA_INPUT);  
   END PROCESS;
end OP1;

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