4-bit shift left reg, Digital Logic Design Consider a 4-bit shift-left register

Question

4-bit shift left reg, Digital Logic Design

Consider a 4-bit shift-left register and the driving signal Xin shown below, where Xin=0 prior to t0 and after t7. QO-3 are Os prior to t0. Note that Xin leads ahead of the clock by At and remains valid for 2 or 1 clocks; Delta t Tclk. Draw the wave forms of QO, Ql, Q2, and Q3 respectively on the timing chart below. For each of the QO-3, what would you describe the timing relationship between Q, and Xin, j=0-3? By the observations from (b), does that give you any idea of conceiving a circuit which would delay the input by 2 clocks (or more precisely, more than 2 but definitely less than 3 clocks)? Write behavior-level description for the module as required.

Explanation / Answer

MM54C95,MM74C95
MM54C95 MM74C95 4-Bit Right-Shift Left-Shift Register
Literature Number: SNOS348A
TL/F/5890
MM54C95/MM74C95 4-Bit Right-Shift Left-Shift Register
February 1988
MM54C95/MM74C95
4-Bit Right-Shift Left-Shift Register
General Description
This 4-bit shift register is a monolithic complementary MOS
(CMOS) integrated circuit composed of four D flip-flops.
This register will perform right-shift or left-shift operations
dependent upon the logical input level to the mode control.
A number of these registers may be connected in series to
form an N-bit right-shift or left-shift register.
When a logical ``0'' level is applied to the mode control input,
the output of each flip-flop is coupled to the D input of
the succeeding flip flop. Right-shift operation is performed
by clocking at the clock 1 input, and serial data entered at
the serial input, clock 2 and parallel inputs A through D are
inhibited. With a logical ``1'' level applied to the mode control,
outputs to succeeding stages are decoupled and parallel
loading is possible, or with external interconnection, shiftleft
operation can be accomplished by connecting the output
of each flip-flop to the parallel input of the previous
flip-flop and serial data is entered at input D.
Features
Y Medium speed operation 10 MHz (typ.)
VCC e 10V, CL e 50 pF
Y High noise immunity 0.45 VCC (typ.)
Y Low power 100 nW/(typ.)
Y Tenth power TTL compatible Drive 2 LTTL loads
Y Wide supply voltage range 3V to 15V
Y Synchronous parallel load
Y Parallel inputs and outputs from each flip-flop
Y Negative edge triggered clocking
Y The MM54C95/MM74C95 follows the MM54L95/
MM74L95 Pinout
Applications
Y Data terminals
Y Instrumentation
Y Automotive
Y Medical electronics
Y Alarm systems
Y Remote metering
Y Industrial electronics
Y Computers
Block and Connection Diagrams
TL/F/5890

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