4. A 7ALVC2074 register is using VCC 2.7V. The Q-bar output is D input. What is

Question

4. A 7ALVC2074 register is using VCC 2.7V. The Q-bar output is D input. What is the maximum clock frequency for this circuit? (n) 100 MH (1s) 106.4 MH () 113.7 MH (d) 134.2 MH e))175 MH 5. Scan teting (a) provides controllability (b) provides observability (c) provides reliability (d) all of the above (e) (a) and (b) 6. LUTs in FPGAs are used to (a) implement counter circuits (b) implement combinational logic circuits (c) implement clock circuits (d) all of the above 7. A FSM has 2 inputs, 3 outputs and 22 states. Which of be used to implement the FSM? (a) GAL22V10 (b) PAL16L8 (c) PAL16R4 (d) PAL16R6 8. You need to convert serial data into parallel data. T (a) a shift register (b) LFSR (c) FSM (d) ring counter

Explanation / Answer

4.(e)

5.(e)

6.(b)

7.(a) GAL22V10 can be used to implement the FSM

8.(a) shift registers are used for convert serial data into parallel data and viceversa

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